Darjn Esposito

According to our database1, Darjn Esposito authored at least 18 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic.
Circuits Syst. Signal Process., 2019

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy.
Circuits Syst. Signal Process., 2019

2018
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Approximate Multipliers Based on New Approximate Compressors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Stall-Aware Fixed-Point Implementation of LMS Filters.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

On the Use of Approximate Multipliers in LMS Adaptive Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Approximate computing in the nanoscale era.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Quality-Scalable Approximate LMS Filter.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design of Low-Power Approximate LMS Filters with Precision-Scalability.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.
IEEE Trans. Computers, 2017

Power-precision scalable latch memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

On the use of approximate adders in carry-save multiplier-accumulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Variable Latency Speculative Han-Carlson Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015


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