Ettore Napoli

According to our database1, Ettore Napoli authored at least 68 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Time Base Option for Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes.
IEEE Trans. Instrum. Meas., 2020

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications.
IEEE Trans. Circuits Syst., 2020

Digital Circuit for Seamless Resampling ADC Output Streams.
Sensors, 2020

Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic.
Circuits Syst. Signal Process., 2019

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy.
Circuits Syst. Signal Process., 2019

Variable-Rounded LMS Filter for Low-Power Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Digital Circuit for the Arbitrary Selection of Sample Rate in Digital Storage Oscilloscopes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Approximate Multipliers Based on New Approximate Compressors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Stall-Aware Fixed-Point Implementation of LMS Filters.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

On the Use of Approximate Multipliers in LMS Adaptive Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Quality-Scalable Approximate LMS Filter.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design of Low-Power Approximate LMS Filters with Precision-Scalability.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.
IEEE Trans. Computers, 2017

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines.
Circuits Syst. Signal Process., 2017

On the use of approximate adders in carry-save multiplier-accumulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Variable Latency Speculative Han-Carlson Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015

Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images.
Integr., 2015

FPGA implementation of the CCSDS-123.0-B-1 lossless Hyperspectral Image compression algorithm prediction stage.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

An FPGA processor for real-time, fixed-point refinement of CDVS keypoints.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

The noise and spur delusion in fractional-N frequency synthesizer design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition.
IEEE Trans. Instrum. Meas., 2014

High Speed Speculative Multipliers Based on Speculative Carry-Save Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Accurate Fixed-Point Logarithmic Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Truncated squarer with minimum mean-square error.
Microelectron. J., 2014

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA.
Integr., 2014

A Frequency Domain Processor for Real-Time CDVS Keypoints Extraction.
Proceedings of the Tenth International Conference on Signal-Image Technology and Internet-Based Systems, 2014

FPGA based system for the generation of noise with programmable power spectrum.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems.
Proceedings of the Sixth International Conference on Digital Image Processing, 2014

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

NORA based TDC in 90 nm CMOS.
Microelectron. J., 2013

FPGA-based architecture for real time segmentation and denoising of HD video.
J. Real Time Image Process., 2013

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video.
J. Electr. Comput. Eng., 2013

Implementation of a pulse-holding Time-to-Digital Converter on an FPGA.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
An FPGA-based Real-time Background Identification Circuit for 1080p Video.
Proceedings of the Eighth International Conference on Signal Image Technology and Internet Based Systems, 2012

FPGA implementation of OpenCV compatible background identification circuit.
Proceedings of the Computational Modelling of Objects Represented in Images, 2012

2011
Design of Fixed-Width Multipliers With Linear Compensation Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.
IEEE Trans. Computers, 2011

2010
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Fixed-width CSD multipliers with minimum mean square error.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel truncated squarer with linear compensation function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed differential resistor ladder for A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Constrained piecewise polinomial approximation for hardware implementation of elementary functions.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low error truncated multipliers for DSP applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Limits and application of the newly proposed deep-depletion SOI LDMOS.
IET Circuits Devices Syst., 2007

Code compression for ARM7 embedded systems.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005
A novel high-speed sense-amplifier-based flip-flop.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A high-speed sense-amplifier based flip-flop.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Direct digital frequency synthesizers with polynomial hyperfolding technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

High-speed direct digital frequency synthesizers in 0.25-μm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
ROM-less direct digital frequency synthesizers exploiting polynomial approximation.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
A reconfigurable 2D convolver for real-time SAR imaging.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

New design of squarer circuits using Booth encoding and folding techniques.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Test pattern generator for hybrid testing of combinational circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Analysis of power dissipation in double edge-triggered flip-flops.
IEEE Trans. Very Large Scale Integr. Syst., 2000

New clock-gating techniques for low-power flip-flops.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000


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