Gerardo Castellano

According to our database1, Gerardo Castellano authored at least 11 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.



In proceedings 
PhD thesis 




An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy.
Circuits Syst. Signal Process., 2019

An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands.
IEEE J. Solid State Circuits, 2018

Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

An Efficient Digital Background Control for Hybrid Transformer-Based Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.
IEEE Trans. Computers, 2017

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines.
Circuits Syst. Signal Process., 2017

A 0.7-2 GHz auxiliary receiver with enhanced compression for SAW-less FDD.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Digital circuit for the generation of colored noise exploiting single bit pseudo random sequence.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low power control system for real-time tuning of a hybrid transformer-based receiver.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016