Nicola Petra

According to our database1, Nicola Petra authored at least 64 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications.
IEEE Trans. Circuits Syst., 2020

Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Self-tunable chaotic true random bit generator in current-mode CMOS circuit with nonlinear distortion analysis.
Int. J. Circuit Theory Appl., 2019

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy.
Circuits Syst. Signal Process., 2019

Piecewise Linear Chaotic Maps in Current Mode CMOS Circuits: Nonlinear Distortion Analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Variable-Rounded LMS Filter for Low-Power Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Approximate Multipliers Based on New Approximate Compressors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Stall-Aware Fixed-Point Implementation of LMS Filters.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

On the Use of Approximate Multipliers in LMS Adaptive Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient Implementation of Recurrent Neural Network Accelerators.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.
IEEE Trans. Computers, 2017

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines.
Circuits Syst. Signal Process., 2017

On the use of approximate adders in carry-save multiplier-accumulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Variable Latency Speculative Han-Carlson Adder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015

Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images.
Integr., 2015

2014
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Accurate Fixed-Point Logarithmic Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Truncated squarer with minimum mean-square error.
Microelectron. J., 2014

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA.
Integr., 2014

Hardware performance versus video quality trade-off for Gaussian mixture model based background identification systems.
Proceedings of the Sixth International Conference on Digital Image Processing, 2014

Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

NORA based TDC in 90 nm CMOS.
Microelectron. J., 2013

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video.
J. Electr. Comput. Eng., 2013

2012
A high-speed differential resistor ladder.
Microelectron. J., 2012

Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies.
Int. J. Circuit Theory Appl., 2012

2011
Design of Fixed-Width Multipliers With Linear Compensation Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Efficient Logarithmic Converters for Digital Signal Processing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations.
IEEE Trans. Computers, 2011

Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error.
IEEE Trans. Computers, 2011

2010
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

Fixed-width CSD multipliers with minimum mean square error.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel truncated squarer with linear compensation function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed differential resistor ladder for A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
High-Performance Special Function Unit for Programmable 3-D Graphics Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 µm CMOS.
IEEE J. Solid State Circuits, 2008

A high performance floating-point special function unit using constrained piecewise quadratic approximation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Constrained piecewise polinomial approximation for hardware implementation of elementary functions.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A high-speed and high-accuracy interpolator for digital modems.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low error truncated multipliers for DSP applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme.
IEEE Trans. Computers, 2007

A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique.
IEEE J. Solid State Circuits, 2007

A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS.
IEEE J. Solid State Circuits, 2007

High Speed Galois Fields GF(2<sup>m</sup>) Multipliers.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Design of fixed-width multipliers with minimum mean square error.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Code compression for ARM7 embedded systems.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A novel high-speed sense-amplifier-based flip-flop.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A high-speed sense-amplifier based flip-flop.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
High-speed direct digital frequency synthesizers in 0.25-μm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


  Loading...