Davide De Caro

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures.

[BibT_eX]

[DOI]

CoRR, 2023

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A novel low-power DLMS adaptive filter with sign-magnitude learning and approximated FIR section.

[BibT_eX]

[DOI]

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

2020

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Low-Power Approximate Multiplier with Error Recovery using a New Approximate 4-2 Compressor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2019

An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2019

Variable-Rounded LMS Filter for Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Approximate Multipliers Based on New Approximate Compressors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands.

[BibT_eX]

[DOI]

Danilo Manstretta

Rinaldo Castello

IEEE J. Solid State Circuits, 2018

Stall-Aware Fixed-Point Implementation of LMS Filters.

[BibT_eX]

[DOI]

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

On the Use of Approximate Multipliers in LMS Adaptive Filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Quality-Scalable Approximate LMS Filter.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design of Low-Power Approximate LMS Filters with Precision-Scalability.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017

Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

An Efficient Digital Background Control for Hybrid Transformer-Based Receivers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A SISO Register Circuit Tailored for Input Data with Low Transition Probability.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2017

On the use of approximate adders in carry-save multiplier-accumulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low power control system for real-time tuning of a hybrid transformer-based receiver.

[BibT_eX]

[DOI]

Gerardo Castellano

Danilo Manstretta

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Variable Latency Speculative Han-Carlson Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images.

[BibT_eX]

[DOI]

Integr., 2015

2014

High Speed Speculative Multipliers Based on Speculative Carry-Save Tree.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Accurate Fixed-Point Logarithmic Converter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Truncated squarer with minimum mean-square error.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA.

[BibT_eX]

[DOI]

Integr., 2014

Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint.

[BibT_eX]

[DOI]

Michele De Martino

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013

Glitch-Free NAND-Based Digitally Controlled Delay-Lines.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error.

[BibT_eX]

[DOI]

Fabio Tessitore

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

NORA based TDC in 90 nm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2013

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2013

2012

An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A high-speed differential resistor ladder.

[BibT_eX]

[DOI]

Marino Coppola

Microelectron. J., 2012

Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2012

2011

Design of Fixed-Width Multipliers With Linear Compensation Function.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Efficient Logarithmic Converters for Digital Signal Processing Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

2010

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS.

[BibT_eX]

[DOI]

Carlo Alberto Romani

Claudio Parrella

IEEE J. Solid State Circuits, 2010

Fixed-width CSD multipliers with minimum mean square error.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel truncated squarer with linear compensation function.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed differential resistor ladder for A/D converters.

[BibT_eX]

[DOI]

Valeria Garofalo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

High-Performance Special Function Unit for Programmable 3-D Graphics Processors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A high performance floating-point special function unit using constrained piecewise quadratic approximation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Constrained piecewise polinomial approximation for hardware implementation of elementary functions.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Low error truncated multipliers for DSP applications.

[BibT_eX]

[DOI]

Valeria Garofalo

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

High Speed Galois Fields GF(2<sup>m</sup>) Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Design of fixed-width multipliers with minimum mean square error.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A novel high-speed sense-amplifier-based flip-flop.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A high-speed sense-amplifier based flip-flop.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

Direct digital frequency synthesizers with polynomial hyperfolding technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

High-speed direct digital frequency synthesizers in 0.25-μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Booth folding encoding for high performance squarer circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Direct digital frequency synthesizers exploiting piecewise linear Chebyshev approximation.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Direct digital frequency synthesis with dual-slope approach.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2003, 2003

2002

Architetture innovative per la sintesi digitale diretta di frequenza.

[BibT_eX]

[DOI]

PhD thesis, 2002

Shuffled serial adder: an area-latency effective serial adder.

[BibT_eX]

[DOI]

Nicola Mazzocca

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

ROM-less direct digital frequency synthesizers exploiting polynomial approximation.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

A reconfigurable 2D convolver for real-time SAR imaging.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

New design of squarer circuits using Booth encoding and folding techniques.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Test pattern generator for hybrid testing of combinational circuits.

[BibT_eX]

[DOI]

Nicola Mazzocca

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

New clock-gating techniques for low-power flip-flops.

[BibT_eX]

[DOI]