David Levacq

According to our database, David Levacq authored at least 7 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2008

Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time.

David Levacq, Makoto Takamiya, Takayasu Sakurai

IEEE J. Solid State Circuits, 2008

1/5 power reduction by global optimization based on fine-grained body biasing.

Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.

David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat

J. Multiple Valued Log. Soft Comput., 2007

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode.

David Levacq, Vincent Dessard, Denis Flandre

IEEE J. Solid State Circuits, 2007

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.

David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.

David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

Ultra-low power flip-flops for MTCMOS circuits.

David Levacq, Vincent Dessard, Denis Flandre

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005