Debaleena Das

According to our database, Debaleena Das authored at least 7 papers between 1997 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2000

Reducing test data volume using external/LBIST hybrid test patterns.

Debaleena Das, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes.

Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999

Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits.

Debaleena Das, Nur A. Touba

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.

Debaleena Das, Nur A. Touba

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fault diagnosis in scan-based BIST using both time and space information.

Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes.

Debaleena Das, Nur A. Touba

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations.

Debaleena Das, Mark G. Karpovsky

J. Electron. Test., 1997