Mark G. Karpovsky

Affiliations:
  • Boston University, MA, USA


According to our database1, Mark G. Karpovsky authored at least 108 papers between 1977 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 1991, "For contributions to techniques and theory for design and testing of circuits and systems.".

Timeline

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Bibliography

2019
Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes.
IET Comput. Digit. Tech., 2019

Bulwark: Securing implantable medical devices communication channels.
Comput. Secur., 2019

2017
A Design of Secure and ReliableWireless Transmission Channel for Implantable Medical Devices.
Proceedings of the 3rd International Conference on Information Systems Security and Privacy, 2017

2016
Design of Reliable and Secure Devices Realizing Shamir's Secret Sharing.
IEEE Trans. Computers, 2016

A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015
Relations Between the Entropy of a Source and the Error Masking Probability for Security-Oriented Codes.
IEEE Trans. Commun., 2015

New byte error correcting codes with simple decoding for reliable cache design.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
Optimal Turn Prohibition for Deadlock Prevention in Networks With Regular Topologies.
IEEE Trans. Control. Netw. Syst., 2014

Design of Strongly Secure Communication and Computation Channels by Nonlinear Error Detecting Codes.
IEEE Trans. Computers, 2014

Hardware Implementation of Secure Shamir's Secret Sharing Scheme.
IACR Cryptol. ePrint Arch., 2014

2013
Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes.
Proceedings of the HASP 2013, 2013

2012
Design of Cryptographic Devices Resilient to Fault Injection Attacks Using Nonlinear Robust Codes.
Proceedings of the Fault Analysis in Cryptography, 2012

Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Reliable and secure memories based on algebraic manipulation correction codes.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011
Robust correction of repeating errors by non-linear codes.
IET Commun., 2011

Algebraic manipulation detection codes and their applications for design of secure cryptographic devices.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks.
IEEE Trans. Parallel Distributed Syst., 2010

Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes.
J. Electron. Test., 2010

Robust FSMs for cryptographic devices resilient to strong fault injection attacks.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

Duplication Based One-to-Many Coding for Trojan HW Detection.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Deadlock prevention by turn prohibition in interconnection networks.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Multilinear codes for robust error detection.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Designing fault tolerant FSM by nano-PLA.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes.
Proceedings of the Information and Communications Security, 11th International Conference, 2009

Replacing linear Hamming codes by robust nonlinear codes results in a reliability improvement of memories.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2008
Asynchronous balanced gates tolerant to interconnect variability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Comparative Analysis of Robust Fault Attack Resistant Architectures for Public and Private Cryptosystems.
Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

2007
Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard.
J. Syst. Archit., 2007

2006
On robust and dynamic identifying codes.
IEEE Trans. Inf. Theory, 2006

A New Algorithm for Finding Minimal Cycle-Breaking Sets of Turns in a Graph.
J. Graph Algorithms Appl., 2006

Power Attacks on Secure Hardware Based on Early Propagation of Data.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

DPA on Faulty Cryptographic Hardware and Countermeasures.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Non-linear Residue Codes for Robust Public-Key Arithmetic.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

2005
Remarks on Calculation of Autocorrelation on Finite Dyadic Groups by Local Transformations of Decision Diagrams.
Proceedings of the Computer Aided Systems Theory, 2005

Delay Insensitive Encoding and Power Analysis: A Balancing Act.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
New Class of Nonlinear Systematic Error Detecting Codes.
IEEE Trans. Inf. Theory, 2004

Spectral Techniques in Binary and Multiple-Valued Switching Theory: A Review of Results in the Decade 1991-2000.
J. Multiple Valued Log. Soft Comput., 2004

Construction of linearly transformed planar BDD by Walsh coefficients.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Scalable Cycle-Breaking Algorithms for Gigabit Ethernet Backbones.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004

Robust Protection against Fault-Injection Attacks on Smart Cards Implementing the Advanced Encryption Standard.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

2003
Application of network calculus to general topologies using turn-prohibition.
IEEE/ACM Trans. Netw., 2003

Data verification and reconciliation with generalized error-control cod.
IEEE Trans. Inf. Theory, 2003

Reduction of Sizes of Decision Diagrams by Autocorrelation Functions.
IEEE Trans. Computers, 2003

Cycles identifying vertices and edges in binary hypercubes and 2-dimensional tori.
Discret. Appl. Math., 2003

2002
Fault Tolerant Unicast Wormhole Routing in Irregular Computer Networks.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Sequential Circuits Applicable for Detecting Different Types of Faults.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Self-checking sequential circuits with self-healing ability.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Spectral Techniques in Binary and Multiple-Valued Switching Theory.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

An Approach for Designing On-Line Testable State Machines.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Synthesis of ASM-based Self-Checking Controllers.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

On the Identification of Vertices and Edges Using Cycles.
Proceedings of the Applied Algebra, 2001

1999
On the Covering of Vertices for Fault Diagnosis in Hypercubes.
Inf. Process. Lett., 1999

Fault-tolerant Message Routing in Computer Networks.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1998
Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework.
VLSI Design, 1998

On a New Class of Codes for Identifying Vertices in Graphs.
IEEE Trans. Inf. Theory, 1998

Fault-Tolerant Message Routing for Multiprocessors.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

1997
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations.
J. Electron. Test., 1997

1996
Transparent random access memory testing for pattern sensitive faults.
J. Electron. Test., 1996

1995
Fault Detection in Multiprocessor Systems and Array Processors.
IEEE Trans. Computers, 1995

Pseudo-exhaustive word-oriented DRAM testing.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Diagnosis by Signature Analysis of Test Responses.
IEEE Trans. Computers, 1994

Transparent Memory Testing for Pattern-Sensitive Faults.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Signature Testability of PLA.
Proceedings of the Field-Programmable Logic, 1994

1993
Design of Self-Diagnostic Boards by Multiple Signature Analysis.
IEEE Trans. Computers, 1993

Detection and Location of Given Sets of Errors by Nonbinary Linear Codes.
Proceedings of the Algebraic Coding, 1993

1992
Multidimensional fourier transforms by systolic architectures.
J. VLSI Signal Process., 1992

Coset error detection in BIST design.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Built-in self-diagnostic by space-time compression of test responses.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Multiple Signature Analysis: A Framework for Built-In Self-Diagnostic.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test.
IEEE Des. Test Comput., 1991

Efficient test generation for built-in self-test boundary-scan template.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Built-In Self-Diagnostic Read-Only-Memories.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Fast Fourier transforms over finite groups by multiprocessor systems.
IEEE Trans. Acoust. Speech Signal Process., 1990

Aliasing Probability for Multiple Input Signature Analyzer.
IEEE Trans. Computers, 1990

Optimal Robust Compression of Test Responses.
IEEE Trans. Computers, 1990

Identification of faulty processing elements by space-time compression of test responses.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
Optimal codes for minimax criterion on error detection.
IEEE Trans. Inf. Theory, 1989

Fault Detection in Combinational Networks by Reed-Muller Transforms.
IEEE Trans. Computers, 1989

1988
A Data Compression Technique for Built-In Self-Test.
IEEE Trans. Computers, 1988

Board-Level Diagnosis by Signature Analysis.
Proceedings of the Proceedings International Test Conference 1988, 1988

1987
Multilevel Logical Networks.
IEEE Trans. Computers, 1987

1986
Statistical and computational performance of a class of generalized Wiener filters.
IEEE Trans. Inf. Theory, 1986

1985
Covering radius - Survey and recent results.
IEEE Trans. Inf. Theory, 1985

1984
An approach to the testing of microprocessors.
Proceedings of the 21st Design Automation Conference, 1984

1983
Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults.
IEEE Trans. Computers, 1983

Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests.
Integr., 1983

Testing Computer Hardware through Data Compression in Space and Time.
Proceedings of the Proceedings International Test Conference 1983, 1983

1982
Universal Tests Detecting Input/Output Faults in Almost All Devices.
Proceedings of the Proceedings International Test Conference 1982, 1982

1981
Weight distribution of translates, covering radius, and perfect codes correcting errors of given weights.
IEEE Trans. Inf. Theory, 1981

An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions.
IEEE Trans. Computers, 1981

1980
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines.
IEEE Trans. Computers, 1980

Detecting bridging and stuck-at faults at input and output pins of standard digital components.
Proceedings of the 17th Design Automation Conference, 1980

1979
Fourier Transform over Finite Groups for Error Detection and Error Correction in Computation Channels
Inf. Control., March, 1979

On the weight distribution of binary linear codes (Corresp.).
IEEE Trans. Inf. Theory, 1979

1978
On subspaces contained in subsets of finite homogeneous spaces.
Discret. Math., 1978

Coordinate density of sets of vectors.
Discret. Math., 1978

1977
Some Optimization Problems for Convolution Systems over Finite Groups
Inf. Control., July, 1977

Harmonic Analysis over Finite Commutative Groups in Linearization Problems For Systems of Logical Functions
Inf. Control., February, 1977

Fast Fourier Transforms on Finite Non-Abelian Groups.
IEEE Trans. Computers, 1977

Error Detection in Digital Devices and Computer Programs with the Aid of Linear Recurrent Equations Over Finite Commutativs Groups.
IEEE Trans. Computers, 1977

Linear Checking Equations and Error-Correcting Capability for Computation Channels.
Proceedings of the Information Processing, 1977


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