Dengjie Wang

According to our database, Dengjie Wang authored at least 6 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS.

Dengjie Wang, Ziqiang Wang, Hao Xu, Jiawei Wang, Zeliang Zhao, Chun Zhang, Zhihua Wang, Hong Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS.

Hong Chen, Dengjie Wang, Ziqiang Wang, Shuai Yuan, Chun Zhang, Zhihua Wang

IEEE Access, 2021

A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS.

Zeliang Zhao, Xin Wu, Dengjie Wang, Ziqiang Wang, Chun Zhang, Xiangyu Li, Zhihua Wang

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2019

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology.

Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes.

Wenhuan Luan, Ting Chen, Shuai Yuan, Peijie Li, Ziqiang Wang, Xin Lin, Mao Li, Dengjie Wang, Hong Chen

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.

Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017