According to our database1, Jianye Wang authored at least 9 papers between 2015 and 2020.
Legend:Book In proceedings Article PhD thesis Other
IEEE J. Solid State Circuits, 2020
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Microelectron. J., 2018
Signal Process., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
The simplest nonconforming mixed finite element method for linear elasticity in the symmetric formulation on n-rectangular grids.
Comput. Math. Appl., 2016
Microsecond-Level Temperature Variation of Logic Circuits and Influences of Infrared Cameras' Parameters on Hardware Trojans Detection.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015