Jianye Wang

According to our database1, Jianye Wang authored at least 9 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

2019
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.
Microelectron. J., 2018

2017
Matrix completion-based MIMO radar imaging with sparse planar array.
Signal Process., 2017

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
The simplest nonconforming mixed finite element method for linear elasticity in the symmetric formulation on n-rectangular grids.
Comput. Math. Appl., 2016

Microsecond-Level Temperature Variation of Logic Circuits and Influences of Infrared Cameras' Parameters on Hardware Trojans Detection.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

2015
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015


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