Deyuan Gao

According to our database1, Deyuan Gao authored at least 12 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2022
Integrating internet of things and mixed reality to teach performance-based architectural design: a case study of shading devices.
Educ. Inf. Technol., 2022

2013
Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Three-Operand Floating-Point Adder.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems.
IEEE Trans. Instrum. Meas., 2011

Global Prefetcher Aggressiveness Control for Chip-Multiprocessor.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

2009
A 71ps-resolution Multi-channel CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications.
Proceedings of the IMAGAPP 2009, 2009

2008
Gaining Flexibility and Performance of Computing Using Tailored Instruction Set and Reconfigurable Architecture.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2005
Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Network on Chip for Parallel DSP Architectures.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005


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