Xiaoya Fan

Orcid: 0000-0002-6190-8077

According to our database1, Xiaoya Fan authored at least 51 papers between 2004 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
More Modalities Mean Better: Vessel Target Recognition and Localization Through Symbiotic Transformer and Multiview Regression.
IEEE Trans. Geosci. Remote. Sens., 2024

2023
ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism.
ACM Trans. Embed. Comput. Syst., November, 2023

A Noise-Driven Heterogeneous Stochastic Computing Multiplier for Heuristic Precision Improvement in Energy-Efficient DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

The Power of Fragmentation: A Hierarchical Transformer Model for Structural Segmentation in Symbolic Music Generation.
IEEE ACM Trans. Audio Speech Lang. Process., 2023

More Perspectives Mean Better: Underwater Target Recognition and Localization with Multimodal Data via Symbiotic Transformer and Multiview Regression.
CoRR, 2023

A Wide Conversion Ratio Three-Level DC-DC Converter With Loop-Free Self-Balancing Technique of Flying Capacitor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

CSDSE: Apply Cooperative Search to Solve the Exploration-Exploitation Dilemma of Design Space Exploration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

2022
A Fully Integrated Single-Stage Wireless Power Receiver With Phase-Shift PWM Control for High Battery-Charging Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Memory-Computing Decoupling: A DNN Multitasking Accelerator With Adaptive Data Arrangement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MemUnison: A Racetrack-ReRAM-Combined Pipeline Architecture for Energy-Efficient in-Memory CNNs.
IEEE Trans. Computers, 2022

An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNs.
IEEE Trans. Computers, 2022

DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms.
Integr., 2022

The Power of Reuse: A Multi-Scale Transformer Model for Structural Dynamic Segmentation in Symbolic Music Generation.
CoRR, 2022

A High-Voltage Inverting Converter Based on COT Controlled Buck Regulator with On-Chip Ripple Compensation Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Current-Injection-Based Flying Capacitor Balancing Circuit for Three-Level DC-DC Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 6.78MHz Regulating Rectifier With Constant On-Time Control for High Resolution and Ultra-Fast Transient Response.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

GaitPretreatment: Robust Pretreatment Strategy for Gait Recognition.
Proceedings of the International Conference on Communications, 2022

2021
Review of machine learning methods for RNA secondary structure prediction.
PLoS Comput. Biol., 2021

Balancing memory-accessing and computing over sparse DNN accelerator via efficient data packaging.
J. Syst. Archit., 2021

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform.
Graph. Vis. Comput., 2021

Hardware architecture design of HEVC entropy decoding.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

A Heterogeneous Stochastic Computing Multiplier for Universally Accurate and Energy-Efficient DNNs.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

A Fully-Integrated Reference-Free Relaxation Oscillator with No Comparators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
ENAS oriented layer adaptive data scheduling strategy for resource limited hardware.
Neurocomputing, 2020

An accurate average inductor current limit method for peak current mode buck DC-DC converters.
IEICE Electron. Express, 2020

A Classification Method for Unrecognized Spatial Disorientation Based on Perceptual Process.
IEEE Access, 2020

2019
Automated epileptic seizure detection based on break of excitation/inhibition balance.
Comput. Biol. Medicine, 2019

A Low-Power Comparator-Less Relaxation Oscillator.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A ZVS Active Rectifier with Adaptive On/Off Delay Compensation for WPT Systems.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting.
J. Circuits Syst. Comput., 2017

2015
A Current Mode Buck/Boost DC-DC Converter With Automatic Mode Transition and Light Load Efficiency Enhancement.
IEICE Trans. Electron., 2015

2014
A High Efficiency Adaptive Current mode Step-up/Step-Down DC-DC Converter with Four Modes for Smooth Transition.
J. Circuits Syst. Comput., 2014

2013
An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transition.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Analog layout retargeting with geometric programming and constrains symbolization method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Multivariate Process Capability Index with Spatial Coefficient Modification.
Proceedings of the Third International Conference on Digital Manufacturing & Automation, 2012

An adaptive vector parallel supported transcendental function unit for stream processor.
Proceedings of the 9th International Conference on Fuzzy Systems and Knowledge Discovery, 2012

Three-Operand Floating-Point Adder.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
Global Prefetcher Aggressiveness Control for Chip-Multiprocessor.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

2009
Tolerating Memory Latency Using a Hardware-Based Active-Pushing Technique.
Proceedings of the International Conference on Embedded Software and Systems, 2009

2008
Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
DAC Circuit with Multi-threshold Voltage for TFT-LCD Driver IC.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Embedded System's Performance Analysis with RTC and QT.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

2005
Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Network on Chip for Parallel DSP Architectures.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

2004
An Efficient Verification Method for Microprocessors Based on the Virtual Machine.
Proceedings of the Embedded Software and Systems, First International Conference, 2004


  Loading...