Jianfeng An

Orcid: 0000-0001-6559-1196

According to our database1, Jianfeng An authored at least 21 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism.
ACM Trans. Embed. Comput. Syst., November, 2023

An improved interaction-and-aggregation network for person re-identification.
Multim. Tools Appl., November, 2023

An Adaptive Interference Removal Framework for Video Person Re-Identification.
IEEE Trans. Circuits Syst. Video Technol., September, 2023

A gated multi-hierarchical feature fusion network for recognizing steel plate surface defects.
Multim. Syst., June, 2023

CSDSE: Apply Cooperative Search to Solve the Exploration-Exploitation Dilemma of Design Space Exploration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

2022
An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNs.
IEEE Trans. Computers, 2022

2021
A Linear NAS Service of ConvNets for Fast Deployment in the Edge of 5G Networks.
IEEE Netw., 2021

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform.
Graph. Vis. Comput., 2021

Fault Tolerant XY-YX Routing Algorithm Supporting Backtracking Strategy for NoC.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

2020
FIG-QEMU: A Fault Inject Platform Supporting Full System Simulation.
Proceedings of the 7th International Conference on Dependable Systems and Their Applications, 2020

2019
A Highly Efficient Heterogeneous Processor for SAR Imaging.
Sensors, 2019

2018
Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.
J. Circuits Syst. Comput., 2018

2016
Unified data authenticated encryption for vehicular communication.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

DRAM write-only-cache for improving lifetime of phase change memory.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Speed up an x86 SAME simulator using synthesizable SystemC timing models.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2013
A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit.
Proceedings of the 16th IEEE International Conference on Computational Science and Engineering, 2013

2012
Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
Global Prefetcher Aggressiveness Control for Chip-Multiprocessor.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

2006
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

2005
Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

2004
An Efficient Verification Method for Microprocessors Based on the Virtual Machine.
Proceedings of the Embedded Software and Systems, First International Conference, 2004


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