Danghui Wang
According to our database1,
Danghui Wang
authored at least 41 papers
between 2004 and 2023.
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Bibliography
2023
A Noise-Driven Heterogeneous Stochastic Computing Multiplier for Heuristic Precision Improvement in Energy-Efficient DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
ExpoNAS: Using Exposure-based Candidate Exclusion to Reduce NAS Space for Heterogeneous Pipeline of CNNs.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
PseudoSC: A Binary Approximation to Stochastic Computing within Latent Operation-Space for Ultra-Lightweight on-Edge DNNs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
MemUnison: A Racetrack-ReRAM-Combined Pipeline Architecture for Energy-Efficient in-Memory CNNs.
IEEE Trans. Computers, 2022
An Automatic-Addressing Architecture With Fully Serialized Access in Racetrack Memory for Energy-Efficient CNNs.
IEEE Trans. Computers, 2022
DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms.
Integr., 2022
2021
Efficient Resource-Aware Convolutional Neural Architecture Search for Edge Computing with Pareto-Bayesian Optimization.
Sensors, 2021
IEEE Netw., 2021
Balancing memory-accessing and computing over sparse DNN accelerator via efficient data packaging.
J. Syst. Archit., 2021
Proceedings of the Smart Computing and Communication - 6th International Conference, 2021
A Hop-Parity-Involved Task Schedule for Lightweight Racetrack-Buffer in Energy-Efficient NoCs.
Proceedings of the Smart Computing and Communication - 6th International Conference, 2021
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
A Heterogeneous Stochastic Computing Multiplier for Universally Accurate and Energy-Efficient DNNs.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Neurocomputing, 2020
A Hot/Cold Task Partition for Energy-Efficient Neural Network Deployment on Heterogeneous Edge Device.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2020
Proceedings of the Algorithms and Architectures for Parallel Processing, 2020
2019
Microprocess. Microsystems, 2019
Future Gener. Comput. Syst., 2019
Proceedings of the 2019 IEEE International Conference on Computational Science and Engineering, 2019
2018
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
计算机科学, 2018
J. Circuits Syst. Comput., 2018
Future Gener. Comput. Syst., 2018
A Thread-Saving Schedule with Graph Analysis for Parallel Deep Learning Applications on Embedded Systems.
Proceedings of the 2018 IEEE International Conference on Smart Cloud, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Similarity-Based Node Distance Exploring and Locality-Aware Shuffle Optimization for Hadoop MapReduce.
Proceedings of the 2017 IEEE International Conference on Smart Cloud, 2017
XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.
Proceedings of the International Conference on Computing, Networking and Communications, 2014
DPA: A data pattern aware error prevention technique for NAND flash lifetime extension.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2006
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006
2005
Proceedings of the Embedded Software and Systems, Second International Conference, 2005
2004
Proceedings of the Embedded Software and Systems, First International Conference, 2004