Dhananjay S. Phatak
According to our database1,
Dhananjay S. Phatak
authored at least 44 papers
between 1993 and 2019.
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Bibliography
2019
The CATS Hackathon: Creating and Refining Test Items for Cybersecurity Concept Inventories.
IEEE Secur. Priv., 2019
PPT: New Low Complexity Deterministic Primality Tests Leveraging Explicit and Implicit Non-Residues. A Set of Three Companion Manuscripts.
CoRR, 2019
2018
IEEE Trans. Educ., 2018
2017
CoRR, 2017
2016
J. Parallel Distributed Comput., 2016
Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016
2014
DoubleMod and SingleMod: Simple Randomized Secret-Key Encryption with Bounded Homomorphicity.
IACR Cryptol. ePrint Arch., 2014
A Preliminary FPGA Implementation and Analysis of Phatak's Quotient-First Scaling Algorithm in the Reduced-Precision Residue Number System.
IACR Cryptol. ePrint Arch., 2014
2013
Spread Identity: A new dynamic address remapping mechanism for anonymity and DDoS defense.
J. Comput. Secur., 2013
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013
A Simulation of Document Detection Methods and Reducing False Positives for Private Stream Searching.
Proceedings of the Data Privacy Management and Autonomous Spontaneous Security, 2013
2012
Location Authentication, Tracking, and Emergency Signaling through Power Line Communication: Designs and Protocols for New Out-of-Band Strategies.
Cryptologia, 2012
2011
A New Paradigm to Approximate Oblivious Data Processing (ODP) for Data Confidentiality in Cloud Computing.
Proceedings of the World Congress on Services, 2011
2010
Proceedings of the 7th International Symposium on Visualization for Cyber Security, 2010
Introducing the Trusted Virtual Environment Module: A New Mechanism for Rooting Trust in Cloud Computing.
Proceedings of the Trust and Trustworthy Computing, Third International Conference, 2010
2006
IEEE Trans. Neural Networks, 2006
2005
Proceedings of the First International Conference on Security and Privacy for Emerging Areas in Communications Networks, 2005
Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
IEEE J. Sel. Areas Commun., 2004
2003
IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping.
Comput. Networks, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2002
Verification caching: towards efficient and secure mobile code execution environments.
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002
Simulation of a Common Access Point for Bluetooth, 802.11 and Wired LANs.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
A Novel Mechanism for Data Streaming Across Multiple IP Links for Improving Throughput and Reliability in Mobile Environments.
Proceedings of the Proceedings IEEE INFOCOM 2002, 2002
Proceedings of the 2002 IEEE International Conference on Fuzzy Systems, 2002
2001
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.
IEEE Trans. Computers, 2001
Analysis of TCP Performance on Wireless Ad Hoc Networks Utilizing Preemptive Maintenance Routing.
Proceedings of the 2001 International Conference on Parallel Processing, 2001
2000
Proceedings of the Proceedings IEEE INFOCOM 2000, 2000
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
1999
Relationship between fault tolerance, generalization and the Vapnik-Chervonenkis (VC) dimension of feedforward ANNs.
Proceedings of the International Joint Conference Neural Networks, 1999
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999
Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999
1998
IEEE Trans. Computers, 1998
1995
IEEE Trans. Neural Networks, 1995
1994
Connectivity and performance tradeoffs in the cascade correlation learning architecture.
IEEE Trans. Neural Networks, 1994
Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains.
IEEE Trans. Computers, 1994
1993
Neural Comput., 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993