Dhananjaya Wijerathne

Orcid: 0000-0003-3181-2514

According to our database1, Dhananjaya Wijerathne authored at least 10 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Accelerating Edge AI with Morpher: An Integrated Design, Compilation and Simulation Framework for CGRAs.
CoRR, 2023

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ChordMap: Automated Mapping of Streaming Applications Onto CGRA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Power-Performance Characterization of TinyML Systems.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

REVAMP: a systematic framework for heterogeneous CGRA realization.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2019
CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA.
ACM Trans. Embed. Comput. Syst., 2019

4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs.
Proceedings of the International Conference on Computer-Aided Design, 2019


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