Rohan Juneja

According to our database, Rohan Juneja authored at least 18 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Data-Driven Dynamic Execution Orchestration Architecture.

Zhenyu Bai, Pranav Dangi, Rohan Juneja, Zhaoying Li, Zhanglu Yan, Huiying Lan, Tulika Mitra

Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

HALO: Hardware-Aware Quantization with Low Critical-Path-Delay Weights for LLM Acceleration.

Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh

Proceedings of the Fortieth AAAI Conference on Artificial Intelligence, 2026

2025

CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs.

Yaswanth Tavva, Rohan Juneja, Trevor E. Carlson, Li-Shiuan Peh

ACM Trans. Reconfigurable Technol. Syst., June, 2025

Nexus Machine: An Active Message Inspired Reconfigurable Architecture for Irregular Workloads.

Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra, Li-Shiuan Peh

CoRR, February, 2025

Nexus Machine: An Energy-Efficient Active Message Inspired Reconfigurable Architecture.

Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Tulika Mitra, Li-Shiuan Peh

Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

Building an Open CGRA Ecosystem for Agile Innovation.

Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning.

Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya Bandara, Rohan Juneja, Cheng Tan, Zhenyu Bai, Tulika Mitra

Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024

A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications.

Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

Proceedings of the 21st International SoC Design Conference, 2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.

Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator.

Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML.

Pranav Dangi, Zhenyu Bai, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra

Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023

BioThings Explorer: a query engine for a federated knowledge graph of biomedical APIs.

Jackson Callaghan, Colleen H. Xu, Jiwen Xin, Marco Alvarado Cano, Anders Riutta, Eric Zhou, Rohan Juneja, Yao Yao, Madhumita Narayan, Kristina Hanspers, Ayushi Agrawal, Alexander R. Pico, Chunlei Wu, Andrew I. Su

Bioinform., September, 2023

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.

Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables.

Mohit Upadhyay, Rohan Juneja, Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication.

Saru Vig, Siew-Kei Lam, Rohan Juneja

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication.

Saru Vig, Rohan Juneja, Siew-Kei Lam

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree.

Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew-Kei Lam, Changhai Ou

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Dynamic NoC platform for varied application needs.

Sidhartha Sankar Rout, Hemanta Kumar Mondal, Rohan Juneja, Sri Harsha Gade, Sujay Deb

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018