Anuj Pathania

Orcid: 0000-0002-5813-7021

Affiliations:
  • University of Amsterdam, The Netherlands
  • Karlsruhe Institute of Technology, Germany (PhD 2018)


According to our database1, Anuj Pathania authored at least 42 papers between 2014 and 2023.

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Bibliography

2023
Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation.
ACM Trans. Embed. Comput. Syst., October, 2023

Estimating the Energy Consumption of Applications in the Computing Continuum with iFogSim.
Proceedings of the High Performance Computing, 2023

Performance Engineering for Graduate Students: a View from Amsterdam.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Analyzing Digital Services Across the Compute Continuum Using iFogSim.
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023

PELSI: Power-Efficient Layer-Switched Inference.
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023

Lifetime Estimation for Core-Failure Resilient Multi-Core Processors.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ChordMap: Automated Mapping of Streaming Applications Onto CGRA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems.
ACM Trans. Archit. Code Optim., 2022

CPU-GPU Layer-Switched Low Latency CNN Inference.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Power-Efficient Heterogeneous Many-Core Design With NCFET Technology.
IEEE Trans. Computers, 2021

Neural Network-Based Performance Prediction for Task Migration on S-NUCA Many-Cores.
IEEE Trans. Computers, 2021

T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores.
IEEE Trans. Computers, 2020

Neural Network Inference on Mobile SoCs.
IEEE Des. Test, 2020

Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA.
ACM Trans. Embed. Comput. Syst., 2019

HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems.
IEEE Embed. Syst. Lett., 2019

High-Throughput CNN Inference on Embedded ARM big.LITTLE Multi-Core Processors.
CoRR, 2019

Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processors.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Prediction-Based Task Migration on S-NUCA Many-Cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Scalable Task Schedulers for Many-Core Architectures.
PhD thesis, 2018

Scalable Dynamic Task Scheduling on Adaptive Many-Core.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Task scheduling for many-cores with S-NUCA caches.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

QoS-aware stochastic power management for many-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Energy Efficiency for Clustered Heterogeneous Multicores.
IEEE Trans. Parallel Distributed Syst., 2017

Optimal Greedy Algorithm for Many-Core Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
IEEE Trans. Computers, 2017

Defragmentation of Tasks in Many-Core Architecture.
ACM Trans. Archit. Code Optim., 2017

Scalable probabilistic power budgeting for many-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Dark silicon management: an integrated and coordinated cross-layer approach.
it Inf. Technol., 2016

Distributed fair scheduling for many-cores.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed scheduling for many-cores using cooperative game theory.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Power management for mobile games on asymmetric multi-cores.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Integrated CPU-GPU Power Management for 3D Mobile Games.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Price theory based power management for heterogeneous multi-cores.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014


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