Li-Shiuan Peh

According to our database1, Li-Shiuan Peh authored at least 133 papers between 1996 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2017, "For contributions to the architecture and design automation of networks-on-chip".

Timeline

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Bibliography

2019
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip.
CoRR, 2019

pH Watch - Leveraging Pulse Oximeters in Existing Wearables for Reusable, Real-time Monitoring of pH in Sweat.
Proceedings of the 17th Annual International Conference on Mobile Systems, 2019

SPECTRUM: a software defined predictable many-core architecture for LTE baseband processing.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
LOCUS: Low-Power Customizable Many-Core Architecture for Wearables.
ACM Trans. Embedded Comput. Syst., 2018

Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
On-Chip Networks, Second Edition
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2017

Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect.
Proceedings of the 54th Annual Design Automation Conference, 2017

Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Dynamic framework for building highly-localized mobile web DTN applications.
Computer Communications, 2016

Towards High-Performance Bufferless NoCs with SCEPTER.
Computer Architecture Letters, 2016

A smartphone-based laser distance sensor for outdoor environments.
Proceedings of the 2016 IEEE International Conference on Robotics and Automation, 2016

Poster abstract: Long-term observation with passive Wi-Fi scanning.
Proceedings of the 24th IEEE International Conference on Network Protocols, 2016

Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automotive V2X on phones: Enabling next-generation mobile ITS apps.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

A universal ordered NoC design platform for shared-memory MPSoC.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip.
IEEE Micro, 2014

Ultralow-Power LED-Enabled On-Chip Optical Communication Designed in the III-Nitride and Silicon CMOS Process Integrated Platform.
IEEE Design & Test, 2014

Similitude: Interfacing a Traffic Simulator and Network Simulator with Emulated Android Clients.
Proceedings of the IEEE 80th Vehicular Technology Conference, 2014

Using mobile phone barometer for low-power transportation context detection.
Proceedings of the 12th ACM Conference on Embedded Network Sensor Systems, 2014

Single-cycle collective communication over a shared network fabric.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A case for leveraging 802.11p for direct phone-to-phone communications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

MobiStreams: A Reliable Distributed Stream Processing System for Mobile Devices.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects.
IEEE Trans. VLSI Syst., 2013

Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks.
IEEE Computer, 2013

Modeling reaction time within a traffic simulation model.
Proceedings of the 16th International IEEE Conference on Intelligent Transportation Systems, 2013

Breaking the on-chip latency barrier using SMART.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.
Proceedings of the Design, Automation and Test in Europe, 2013

SMART: a single-cycle reconfigurable NoC for SoC applications.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
ORION 2.0: A Power-Area Simulator for Interconnection Networks.
IEEE Trans. VLSI Syst., 2012

Leveraging Smartphone Cameras for Collaborative Road Advisories.
IEEE Trans. Mob. Comput., 2012

Dynamic QoS management for chip multiprocessors.
TACO, 2012

Low cost crowd counting using audio tones.
Proceedings of the 10th ACM Conference on Embedded Network Sensor Systems, 2012

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

A distributed taxi advisory system.
Proceedings of the 12th International Conference on ITS Telecommunications, 2012

Meteor Shower: A Reliable Stream Processing System for Commodity Data Centers.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System Using Real Application Workloads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

DIPLOMA: Consistent and coherent shared memory over mobile phones.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs.
J. Parallel Distrib. Comput., 2011

RegReS: Adaptively maintaining a target density of regional services in opportunistic vehicular networks.
Proceedings of the Ninth Annual IEEE International Conference on Pervasive Computing and Communications, 2011

Demo: SignalGuru: leveraging mobile phones for collaborative traffic signal schedule advisory.
Proceedings of the 9th International Conference on Mobile Systems, 2011

SignalGuru: leveraging mobile phones for collaborative traffic signal schedule advisory.
Proceedings of the 9th International Conference on Mobile Systems, 2011

Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

A systematic methodology to develop resilient cache coherence protocols.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

A low-swing crossbar and link generator for low-power networks-on-chip.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips.
Proceedings of the 48th Design Automation Conference, 2011

Enabling system-level modeling of variation-induced faults in networks-on-chips.
Proceedings of the 48th Design Automation Conference, 2011

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Design of a High-Throughput Distributed Shared-Buffer NoC Router.
Proceedings of the NOCS 2010, 2010

Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.
Proceedings of the NOCS 2010, 2010

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS.
Proceedings of the 28th International Conference on Computer Design, 2010

Adaptive spatiotemporal node selection in dynamic networks.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
On-Chip Networks
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2009

On-Chip Networks for Multicore Systems.
Proceedings of the Multicore Processors and Systems, 2009

Special Section on International Symposium on Networks-on-Chip (NOCS).
IEEE Trans. VLSI Syst., 2009

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Express Virtual Channels with Capacitively Driven Global Links.
IEEE Micro, 2009

A High-Throughput Distributed Shared-Buffer NoC Router.
Computer Architecture Letters, 2009

In-network coherence filtering: snoopy coherence without broadcasts.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

GARNET: A detailed on-chip network model inside a full-system simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
System-Level Dynamic Thermal Management for High-Performance Microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Toward Ideal On-Chip Communication Using Express Virtual Channels.
IEEE Micro, 2008

Thousand-Core Chips [Roundtable].
IEEE Design & Test of Computers, 2008

Guest Editors' Introduction: Tackling Key Problems in NoCs.
IEEE Design & Test of Computers, 2008

Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Token flow control.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

A system-level perspective for efficient NoC design.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Extending open core protocol to support system-level cache coherence.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Leveraging on-chip networks for data cache migration in chip multiprocessors.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.
IEEE Trans. VLSI Syst., 2007

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems.
IEEE Trans. VLSI Syst., 2007

Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst., 2007

Software-directed power-aware interconnection networks.
TACO, 2007

Predicting link quality using supervised learning in wireless sensor networks.
Mobile Computing and Communications Review, 2007

Research Challenges for On-Chip Interconnection Networks.
IEEE Micro, 2007

Guest Editors' Introduction: On-Chip Interconnects for Multicores.
IEEE Micro, 2007

Circuit-Switched Coherence.
Computer Architecture Letters, 2007

Express virtual channels: towards the ideal interconnection fabric.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Temperature-Aware On-Chip Networks.
IEEE Micro, 2006

In-network cache coherence.
Computer Architecture Letters, 2006

Transport layer approaches for improving idle energy in challenged sensor networks.
Proceedings of the 2006 SIGCOMM workshop on Challenged networks, 2006

Supervised Learning in Sensor Networks: New Approaches with Routing, Reliability Optimizations.
Proceedings of the Third Annual IEEE Communications Society Conference on Sensor, 2006

A supervised learning approach for routing optimizations in wireless sensor networks.
Proceedings of the 2nd international workshop on Multi-hop ad hoc networks: from theory to reality, 2006

Situation-Aware Caching Strategies in Highly Varying Mobile Networks.
Proceedings of the 14th International Symposium on Modeling, 2006

A Statistical Traffic Model for On-Chip Interconnection Networks.
Proceedings of the 14th International Symposium on Modeling, 2006

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

HybDTM: a coordinated hardware-software approach for dynamic thermal management.
Proceedings of the 43rd Design Automation Conference, 2006

High-level power analysis for multi-core chips.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
Guest Editorial: Special Section on On-Chip Networks.
IEEE Trans. Parallel Distrib. Syst., 2005

Hardware-modulated parallelism in chip multiprocessors.
SIGARCH Computer Architecture News, 2005

Formal Control Techniques for Power-Performance Management.
IEEE Micro, 2005

Achieving Structural and Composable Modeling of Complex Systems.
International Journal of Parallel Programming, 2005

A new scheme on link quality prediction and its applications to metric-based routing.
Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, 2005

Coordinated, distributed, formal energy management of chip multiprocessors.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks.
Proceedings of the 2005 Design, 2005

2004
MARio: mobility-adaptive routing using route lifetime abstractions in mobile ad hoc networks.
Mobile Computing and Communications Review, 2004

Thermal Modeling, Characterization and Management of On-Chip Networks.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Achieving Structural and Composable Modeling of Complex Systems.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Design-Space Exploration of Power-Aware On/Off Interconnection Networks.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

High-level power analysis for on-chip networks.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.
IEEE Micro, 2003

Power-driven Design of Router Microarchitectures in On-chip Networks.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Leakage power modeling and optimization in interconnection networks.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Dynamic power management for power optimization of interconnection networks using on/off links.
Proceedings of the 11th Annual IEEE Symposium on High Performance Interconnects, 2003

2002
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links.
Computer Architecture Letters, 2002

Orion: a power-performance simulator for interconnection networks.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Design Tools for Application Specific Embedded Processors.
Proceedings of the Embedded Software, Second International Conference, 2002

Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2001
A Delay Model for Router Microarchitectures.
IEEE Micro, 2001

A Delay Model and Speculative Architecture for Pipelined Routers.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Flit-Reservation Flow Control.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1997
Domain-Specific Semantic Class Disambiguation Using WordNet.
Proceedings of the Fifth Workshop on Very Large Corpora, 1997

1996
A Divide-and-Conquer Strategy for Parsing
CoRR, 1996


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