Donghyun Han

Orcid: 0000-0002-2385-2375

According to our database1, Donghyun Han authored at least 16 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture.
Proceedings of the 20th International SoC Design Conference, 2023

2022
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory.
IEEE Access, 2021

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory.
IEEE Access, 2021

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure.
Proceedings of the 18th International SoC Design Conference, 2021

A Circular-based TSV Repair Architecture.
Proceedings of the 18th International SoC Design Conference, 2021

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.
Proceedings of the 18th International SoC Design Conference, 2021

2020
W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.
Proceedings of the IEEE International Test Conference in Asia, 2020

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair.
Proceedings of the International SoC Design Conference, 2020

2019
Dynamic Built-In Redundancy Analysis for Memory Repair.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
3D Memory Formed of Unrepairable Memory Dice and Spare Layer.
Proceedings of the TENCON 2018, 2018

2017
A new repair scheme for TSV-based 3D memory using base die repair cells.
Proceedings of the International SoC Design Conference, 2017


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