Sooryeong Lee

According to our database, Sooryeong Lee authored at least 7 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A New Fail Address Memory Architecture for Cost-Effective ATE.

Hayoung Lee, Sooryeong Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

2023

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.

Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

An Improved Early Termination Methodology Using Convolutional Neural Network.

Seung Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

FAME: Fault Address Memory Structure for Repair Time Reduction.

Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

PROG: Per-Row Output Generator for BOST.

Sooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

2021

A Circular-based TSV Repair Architecture.

Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang

Proceedings of the 18th International SoC Design Conference, 2021

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.

Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang

Proceedings of the 18th International SoC Design Conference, 2021