Sooryeong Lee

According to our database, Sooryeong Lee authored at least 15 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing.

Sooryeong Lee, Juyong Lee, Hayoung Lee, Sungho Kang

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026

A Dual-Mode Online BISR Architecture for Interconnect and Memory Repair in Chiplet-Based Systems.

Donghyun Han, Sooryeong Lee, Jongho Park, Dayoung Kim, Seungtae Kim, Youngkwang Lee, Sungho Kang

IEEE Trans. Reliab., 2026

2025

A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing.

Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., March, 2025

A New Pipelined Output Data Reducer of BOST for Improved Parallelism.

Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

2024

A New ISA for High-Speed and Area-Efficient ALPG.

Juyong Lee, Hayoung Lee, Sooryeong Lee, Sungho Kang

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

RA-Aware Fail Data Collection Architecture for Cost Reduction.

Hayoung Lee, Sooryeong Lee, Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

A New Fail Address Memory Architecture for Cost-Effective ATE.

Hayoung Lee, Sooryeong Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

APAPG: Address Pre-Processed ALPG for High-Speed Linear Test.

Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang

Proceedings of the 21st International SoC Design Conference, 2024

Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis.

Juyong Lee, Sooryeong Lee, Hayoung Lee, Sungho Kang

Proceedings of the 21st International SoC Design Conference, 2024

2023

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.

Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

An Improved Early Termination Methodology Using Convolutional Neural Network.

Seung Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

FAME: Fault Address Memory Structure for Repair Time Reduction.

Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

PROG: Per-Row Output Generator for BOST.

Sooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

2021

A Circular-based TSV Repair Architecture.

Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang

Proceedings of the 18th International SoC Design Conference, 2021

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.

Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang

Proceedings of the 18th International SoC Design Conference, 2021