Dongrong Zhang

Orcid: 0000-0001-5351-592X

According to our database1, Dongrong Zhang authored at least 12 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
On-Chip Structures for Fmax Binning and Optimization.
Sensors, 2022

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2022

A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC.
Proceedings of the IEEE International Test Conference in Asia, 2022

2021
A Novel Authentication Methodology to Detect Counterfeit PCB Using PCB Trace-Based Ring Oscillator.
IEEE Access, 2021

Collaborative Mechanism for Public Digital Preservation Service in China.
Proceedings of the 17th International Conference on Digital Preservation, 2021

An On-chip Path Delay Measurement Sensor for Aging Monitoring.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2018
An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Secure Scan and Test Using Obfuscation Throughout Supply Chain.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

AES Design Improvements Towards Information Security Considering Scan Attack.
Proceedings of the 17th IEEE International Conference On Trust, 2018

2017
Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

DOST: Dynamically obfuscated wrapper for split test against IC piracy.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016


  Loading...