LeRoy Winemberg

Affiliations:
  • Intel Corp., Hillsboro, OR, USA
  • NXP Semiconductors, Austin, TX, USA


According to our database1, LeRoy Winemberg authored at least 38 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2021
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops.
ACM Trans. Design Autom. Electr. Syst., 2021

2019
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection.
Proceedings of the 24th IEEE European Test Symposium, 2019

2017
Design of Reliable SoCs With BIST Hardware and Machine Learning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Learning the process for correlation analysis.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Some considerations on choosing an outlier method for automotive product lines.
Proceedings of the IEEE International Test Conference, 2017

Built-in self-test for stability measurement of low dropout regulator.
Proceedings of the IEEE International Test Conference, 2017

Evaluation of loop transfer function based dynamic testing of LDOs.
Proceedings of the International Test Conference in Asia, 2017

2016
A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Test-point insertion efficiency analysis for LBIST applications.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture.
Proceedings of the 2016 IEEE International Test Conference, 2016

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.
Proceedings of the 2016 IEEE International Test Conference, 2016

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Generalization of an outlier model into a "global" perspective.
Proceedings of the 2015 IEEE International Test Conference, 2015

LBIST pattern reduction by learning ATPG test cube properties.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Speed Binning Using Machine Learning And On-chip Slack Sensors.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Predictive LBIST model and partial ATPG for seed extraction.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

On-chip sensor selection for effective speed-binning.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electron. Test., 2013

Fault analysis and simulation of large scale industrial mixed-signal circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements.
Proceedings of the 2012 IEEE International Test Conference, 2012

Screening customer returns with multivariate test analysis.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Special session: Hot topic: Smart silicon.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Special session 5B: Panel How much toggle activity should we be testing with?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Understanding customer returns from a test perspective.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Case Study: Efficient SDD test generation for very large integrated circuits.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Forward prediction based on wafer sort data - A case study.
Proceedings of the 2011 IEEE International Test Conference, 2011

Critical Fault-Based Pattern Generation for Screening SDDs.
Proceedings of the 16th European Test Symposium, 2011

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.
Proceedings of the Design, Automation and Test in Europe, 2011

In-field aging measurement and calibration for power-performance optimization.
Proceedings of the 48th Design Automation Conference, 2011

2010
Detecting and diagnosing open defects.
Proceedings of the 2011 IEEE International Test Conference, 2010

2005
Outsourcing DFT: it can be done but it isn't easy.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005


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