Kangwei Xu

Orcid: 0000-0003-4221-6830

According to our database1, Kangwei Xu authored at least 16 papers between 2022 and 2026.

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Timeline

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Bibliography

2026
HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst., July, 2026

2025
CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference.
CoRR, November, 2025

Large Language Models (LLMs) for Electronic Design Automation (EDA).
CoRR, August, 2025

TeroSeek: An AI-Powered Knowledge Base and Retrieval Generation Platform for Terpenoid Research.
CoRR, May, 2025

Testing and fault tolerance techniques for carbon nanotube-based FPGAs.
Integr., 2025

Accelerated Multi-Key Homomorphic Encryption via Automorphism-Based Circuit Bootstrapping.
IEEE Access, 2025

Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Large Language Models (LLMs) for Verification, Testing, and Design.
Proceedings of the IEEE European Test Symposium, 2025

2024
LLM-Aided Efficient Hardware Design Automation.
CoRR, 2024

Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Logic Design of Neural Networks for High-Throughput and Low-Power Applications.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2022
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2022

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2022

Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022


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