Duoli Zhang

Orcid: 0000-0002-9515-2829

According to our database¹, Duoli Zhang authored at least 20 papers between 2008 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

An Efficient Ring Polynomial Multiplication Accelerator for Homomorphic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023

A Memory-Constraint-Aware List Scheduling Algorithm for Memory-Constraint Heterogeneous Muti-Processor System.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., April, 2023

2022

A communication-aware and predictive list scheduling algorithm for network-on-chip based heterogeneous muti-processor system-on-chip.

[BibT_eX]

[DOI]

Microelectron. J., 2022

RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

2021

A Real-Time Effective Fusion-Based Image Defogging Architecture on FPGA.

[BibT_eX]

[DOI]

ACM Trans. Multim. Comput. Commun. Appl., 2021

Design and Implementation of A High-speed Configurable 2D ML-CFAR Detector.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A low-latency DMM-1 encoder for 3D-HEVC.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2020

2019

SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Efficient Softmax Hardware Architecture for Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2017

On the Accuracy of Stochastic Delay Bound for Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

A chain-multiplier for large scale matrix multiplication.

[BibT_eX]

[DOI]

Can Wei

Yu-Kun Song

Duoli Zhang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design and implementation of homogeneous multi-core system.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2011

Meshim: A high-level performance simulation platform for three-dimensional network-on-chip.

[BibT_eX]

[DOI]

Menwang Xie

Duoli Zhang

Yao Li

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Application-level pipelining on Hierarchical NoC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

VLSI Architecture of Video Post-Processing System for MPEG/H.26X.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

2008

Scalability Study on Mesh Based Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the PACIIA 2008, 2008

A technique of automatic monitor generation based on FSM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Duoli Zhang

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...