Yongsheng Yin

According to our database1, Yongsheng Yin authored at least 17 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Fully Digital Calibration Technique for Channel Mismatch of TIADC at Any Frequency.
IEICE Trans. Electron., March, 2023

An Area-Efficient Large Integer NTT-Multiplier Using Discrete Twiddle Factor Approach.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2022
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree.
ACM Trans. Reconfigurable Technol. Syst., 2022

All-digital calibration algorithm based on channel multiplexing for TI-ADCs.
Microelectron. J., 2022

2021
A fully digital mismatch calibration algorithm for Time-Interleaved ADCs.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Application of 3D laser scanning technology for image data processing in the protection of ancient building sites through deep learning.
Image Vis. Comput., 2020

A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC.
Integr., 2020

Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data.
IEICE Electron. Express, 2020

Risk Analysis of ERP in FY Coal-fired Power Enterprises.
Proceedings of the ICMSS 2020: 2020 4th International Conference on Management Engineering, 2020

2019
A Low Noise Sub-Gigahertz Fractional-N Frequency Generator with Cascaded FIR.
J. Circuits Syst. Comput., 2019

A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs.
IEICE Electron. Express, 2019

NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Efficient Softmax Hardware Architecture for Deep Neural Networks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2017
All-digital background calibration technique for timing mismatch of time-interleaved ADCs.
Integr., 2017

2011
Calibration method considering second-order error term of timing skew for a novel multi-channel ADC.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2007
On the Implementation of Virtual Array Using Configuration Plane.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007


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