Gaoming Du

Orcid: 0000-0002-6730-3167

According to our database1, Gaoming Du authored at least 27 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An Efficient Ring Polynomial Multiplication Accelerator for Homomorphic Encryption.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
An Area-Efficient Large Integer NTT-Multiplier Using Discrete Twiddle Factor Approach.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2022
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree.
ACM Trans. Reconfigurable Technol. Syst., 2022

RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC.
IEEE Des. Test, 2022

2021
A Real-Time Effective Fusion-Based Image Defogging Architecture on FPGA.
ACM Trans. Multim. Comput. Commun. Appl., 2021

Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A low-latency DMM-1 encoder for 3D-HEVC.
J. Real Time Image Process., 2020

Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC.
J. Circuits Syst. Comput., 2020

2019
SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.
ACM J. Emerg. Technol. Comput. Syst., 2019

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness.
Integr., 2019

NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Efficient Softmax Hardware Architecture for Deep Neural Networks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2017
A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC.
J. Circuits Syst. Comput., 2017

On the Accuracy of Stochastic Delay Bound for Network on Chip.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).
Proceedings of the 2017 International Conference on Compilers, 2017

2016
AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip.
J. Circuits Syst. Comput., 2016

OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

2012
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2010
Application-level pipelining on Hierarchical NoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
VLSI Architecture of Video Post-Processing System for MPEG/H.26X.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

2008
Scalability Study on Mesh Based Network on Chip.
Proceedings of the PACIIA 2008, 2008

Study on the Multi-pipeline Reconfigurable Computing System.
Proceedings of the International Conference on Computer Science and Software Engineering, 2008

A technique of automatic monitor generation based on FSM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
On the Implementation of Virtual Array Using Configuration Plane.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007


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