Eiji Fujiwara
According to our database1,
Eiji Fujiwara
authored at least 50 papers
between 1982 and 2010.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1997, "For contributions to the theory and design of error-control codes for computer systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
2009
Int. J. Comput. Appl. Technol., 2009
<i>M</i>-Ary Substitution/Deletion/Insertion/Adjacent-Symbol-Transposition Error Correcting Codes for Data Entry Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Class of Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
2007
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.
Syst. Comput. Jpn., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the IEEE International Symposium on Information Theory, 2007
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the Applied Algebra, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
A class of error control codes for M-spotty byte errors occurred in a limited number of bytes.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
IEEE Trans. Computers, 2004
Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004
2003
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes.
IEEE Trans. Computers, 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Random Double Bit Error Correcting-Single <i>b</i>-<i>bit</i> Byte Error Correcting (DEC-S<sub>b</sub>EC) Codes for Memory Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
2001
Syst. Comput. Jpn., 2001
Proceedings of the 2001 IEEE Information Theory Workshop, 2001
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
1999
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
1998
IEEE Trans. Computers, 1998
1997
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-.
IEEE Trans. Computers, 1997
1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation.
IEICE Trans. Inf. Syst., 1995
Proceedings of the Digest of Papers: FTCS-25, 1995
1994
IEEE Trans. Inf. Theory, 1994
1993
Proceedings of the Digest of Papers: FTCS-23, 1993
A Probabilistic Measurement for Totally Self-Checking Circuits.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Single <i>b</i>-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems.
Proceedings of the Digest of Papers: FTCS-22, 1992
1990
1989
Error-control coding for computer systems.
Prentice Hall, ISBN: 978-0-13-284068-2, 1989
1988
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988
1987
IEEE Trans. Computers, 1987
1984
IEEE Trans. Computers, 1984
1982
IEEE Trans. Computers, 1982