Kazuteru Namba

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022

Low Power Neural Network by Reducing SRAM Operating Voltage.

[BibT_eX]

[DOI]

IEEE Access, 2022

Stuck-at Fault Tolerance in DNN Using Statistical data.

[BibT_eX]

[DOI]

Tomohiro Ishii

Proceedings of the 27th IEEE Pacific Rim International Symposium on Dependable Computing, 2022

A Double Node Upset tolerant SR latch using C-element.

[BibT_eX]

[DOI]

Shogo Takahashi

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

2021

Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory.

[BibT_eX]

[DOI]

Keisuke Kozu

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

2020

Complete Double Node Upset Tolerant Latch Using C-Element.

[BibT_eX]

[DOI]

Yuta Yamamoto

IEICE Trans. Inf. Syst., 2020

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2020

Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses.

[BibT_eX]

[DOI]

Tomohiro Takahashi

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element.

[BibT_eX]

[DOI]

Yuta Yamamoto

Josaphat Tetuko Sri Sumantyo

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017

L band circularly polarized SAR onboard microsatellite.

[BibT_eX]

[DOI]

Nobuyoshi Imura

Shunsuke Onishi

Tetsuo Yasaka

Robertus Heru Triharjanto

Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017

2016

A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

A Calibration Technique for DVMC with Delay Time Controllable Inverter.

[BibT_eX]

[DOI]

Ri Cui

IPSJ Trans. Syst. LSI Des. Methodol., 2016

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Construction of a soft error (SEU) hardened Latch with high critical charge.

[BibT_eX]

[DOI]

Hiroki Ueno

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

2015

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

New 4T-based DRAM cell designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA.

[BibT_eX]

[DOI]

Nobuhide Takashina

IEICE Trans. Inf. Syst., 2013

Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.

[BibT_eX]

[DOI]

Takashi Katagiri

J. Electron. Test., 2013

Extending Non-Volatile Operation to DRAM Cells.

[BibT_eX]

[DOI]

IEEE Access, 2013

A novel scheme for concurrent error detection of OLS parallel decoders.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Testing of switch blocks in TSV-reduced Three-Dimensional FPGA.

[BibT_eX]

[DOI]

Kouta Maebashi

Masato Kitakami

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Improving small-delay fault coverage for on-chip delay measurement.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Dual-edge-triggered FF with timing error detection capability.

[BibT_eX]

[DOI]

Takashi Katagiri

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

NoC Dynamically Reconfigurable as TAM.

[BibT_eX]

[DOI]

Takieddine Sbiai

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture.

[BibT_eX]

[DOI]

Kiyonori Matsumoto

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Construction of BILBO FF with Soft-Error-Tolerant Capability.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

2010

Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.

[BibT_eX]

[DOI]

Takashi Ikeda

IEEE Trans. Very Large Scale Integr. Syst., 2010

Single-Event-Upset Tolerant RS Flip-Flop with Small Area.

[BibT_eX]

[DOI]

Kengo Nakashima

IEICE Trans. Inf. Syst., 2010

Chiba Scan Delay Fault Testing with Short Test Application Time.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

Quantitative Evaluation of Integrity for Remote System Using the Internet.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Single Event Induced Double Node Upset Tolerant Latch.

[BibT_eX]

[DOI]

Masatoshi Sakata

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Soft Error Tolerant BILBO FF.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability.

[BibT_eX]

[DOI]

Shuangyu Ruan

IEICE Trans. Inf. Syst., 2009

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Design for Delay Fault Testability of 2-Rail Logic Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.

[BibT_eX]

[DOI]

Yoshikazu Matsui

J. Electron. Test., 2009

Dependability Evaluation for Internet-Based Remote Systems.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Testing of Switch Blocks in Three-Dimensional FPGA.

[BibT_eX]

[DOI]

Takumi Hoshi

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Delay Measurement Technique Using Signature Registers.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2008

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.

[BibT_eX]

[DOI]

Yoichi Sasaki

J. Electron. Test., 2008

Path Delay Fault Test Set for Two-Rail Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

Soft Error Hardened FF Capable of Detecting Wide Error Pulse.

[BibT_eX]

[DOI]

Shuangyu Ruan

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Delay Fault Testability on Two-Rail Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2007

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.

[BibT_eX]

[DOI]

Takashi Ikeda

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Redundant Design for Wallace Multiplier.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Proposal of Testable Multi-Context FPGA Architecture.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.

[BibT_eX]

[DOI]

Yoichi Sasaki

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Scan Design for Two-Pattern Test without Extra Latches.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Design of Defect Tolerant Wallace Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

2002

Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

A class of systematic m-ary single-symbol error correcting codes.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2001

Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.

[BibT_eX]

[DOI]