Masashi Horiguchi

According to our database, Masashi Horiguchi authored at least 13 papers between 1994 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Simple Reference Voltage Generation Circuit Insensitive to Temperature.

Lei Sha, Anna Kuwana, Masashi Horiguchi, Haruo Kobayashi

Proceedings of the International SoC Design Conference, 2020

2012

A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation.

Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Nanoscale Memory Repair

Masashi Horiguchi, Kiyoo Itoh

Integrated Circuits and Systems, Springer, ISBN: 978-1-4419-7958-2, 2011

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2007

Ultra-Low Voltage Nano-Scale Memories

Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-68853-4, 2007

Low-voltage limitations of memory-rich nano-scale CMOS LSIs.

Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Ultra-low voltage nano-scale embedded RAMs.

Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2003

Review and future prospects of low-voltage RAM circuits.

Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh

IBM J. Res. Dev., 2003

1995

Low-noise, high-speed data transmission using a ringing-canceling output buffer.

Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki

IEEE J. Solid State Circuits, December, 1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

IEEE J. Solid State Circuits, November, 1995

1994

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, August, 1994

Subthreshold-current reduction circuits for multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1994

A charge recycle refresh for Gb-scale DRAM's in file applications.

Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, June, 1994