Masakazu Aoki

According to our database, Masakazu Aoki authored at least 13 papers between 1993 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis.

Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda

IEICE Trans. Electron., 2008

2005

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip.

Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda

IEICE Trans. Electron., 2005

Approach for physical design in sub-100 nm era.

Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Challenge: variability characterization and modeling for 65- to 90-nm processes.

Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

IEEE J. Solid State Circuits, 1999

1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.

Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana

IEEE J. Solid State Circuits, 1998

1995

Low-noise, high-speed data transmission using a ringing-canceling output buffer.

Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki

IEEE J. Solid State Circuits, December, 1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

IEEE J. Solid State Circuits, November, 1995

1994

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, August, 1994

Subthreshold-current reduction circuits for multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1994

A charge recycle refresh for Gb-scale DRAM's in file applications.

Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, June, 1994

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.

Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa

IEEE J. Solid State Circuits, April, 1994

1993

A single 1.5-V digital chip for a 10⁶ synapse neural network.

Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito

IEEE Trans. Neural Networks, 1993