Emre Kultursay

According to our database1, Emre Kultursay authored at least 18 papers between 2010 and 2016.

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Bibliography

2016
Memory Partitioning in the Limit.
Int. J. Parallel Program., 2016

2015
Optimizing off-chip accesses in multicores.
Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2015

2014
Improved cache utilization and preconditioner efficiency through use of a space-filling curve mesh element- and vertex-reordering technique.
Eng. Comput., 2014

2013
Steep-Slope Devices: From Dark to Dim Silicon.
IEEE Micro, 2013

Evaluating STT-RAM as an energy-efficient main memory alternative.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Compiler-Based Data Prefetching and Streaming Non-temporal Store Generation for the Intel(R) Xeon Phi(TM) Coprocessor.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Meeting midway: Improving CMP performance with memory-side prefetching.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Automatic Parallel Code Generation for NUFFT Data Translation on multicores.
J. Circuits Syst. Comput., 2012

Addressing End-to-End Memory Access Latency in NoC-Based Multicores.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Design space exploration of workload-specific last-level caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Off-chip access localization for NoC-based multicores.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Cooperative parallelization.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

A helper thread based dynamic cache partitioning scheme for multithreaded applications.
Proceedings of the 48th Design Automation Conference, 2011

2010
Scalable Parallelization Strategies to Accelerate NuFFT Data Translation on Multicores.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

Code Scheduling for Optimizing Parallelism and Data Locality.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010


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