Kemal Ebcioglu

According to our database1, Kemal Ebcioglu authored at least 57 papers between 1980 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud.
ACM Trans. Reconfigurable Technol. Syst., 2022

Cloud Building Block Chip for Creating FPGA and ASIC Clouds.
ACM Trans. Reconfigurable Technol. Syst., 2022

A parallel hardware hypervisor for hardware-accelerated cloud computing.
Concurr. Comput. Pract. Exp., 2022

2016
Memory Partitioning in the Limit.
Int. J. Parallel Program., 2016

2014
Author retrospective for a <i>global</i> resource-constrained parallelization technique.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2007
Efficient Register Mapping and Allocation in LaTTe, an Open-Source Java Just-in-Time Compiler.
IEEE Trans. Parallel Distributed Syst., 2007

2005
Lightweight monitors for the Java virtual machine.
Softw. Pract. Exp., 2005

Selective sweeping.
Softw. Pract. Exp., 2005

Programming by sketching for bit-streaming programs.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

X10: an object-oriented approach to non-uniform cluster computing.
Proceedings of the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2005

2004
<i>V</i>LaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation.
IEICE Trans. Inf. Syst., 2004

Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2002
Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.
IEEE Trans. Computers, 2002

A Register File Architecture and Compilation Scheme for Clustered ILP Processors.
Proceedings of the Euro-Par 2002, 2002

2001
Dynamic Binary Translation and Optimization.
IEEE Trans. Computers, 2001

Advances and future challenges in binary translation and optimization.
Proc. IEEE, 2001

CARS: A New Code Generation Framework for Clustered ILP Processors.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

A Prolog Tailoring Technique on an Epilog Tailored Procedure.
Proceedings of the Perspectives of System Informatics, 2001

2000
Reducing virtual call overheads in a Java VM just-in-time compiler.
SIGARCH Comput. Archit. News, 2000

Reducing Sweep Time for a Nearly Empty Heap.
Proceedings of the POPL 2000, 2000

Efficient Java exception handling in just-in-time compilation.
Proceedings of the ACM 2000 Java Grande Conference, San Francisco, CA, USA, 2000

Unroll-based register coalescing.
Proceedings of the 14th international conference on Supercomputing, 2000

Binary translation and architecture convergence issues for IBM system/390.
Proceedings of the 14th international conference on Supercomputing, 2000

Instruction-Level Parallelism and Processor Architecture.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Lightweight monitor for Java VM.
SIGARCH Comput. Archit. News, 1999

Optimizations and Oracle Parallelism with Dynamic Translation.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Execution-Based Scheduling for VLIW Architectures.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
The Performance Impact of Exploiting Branch ILP with Tree Representation of ILP Code.
Comput. J., 1998

An eight-issue tree-VLIW processor for dynamic binary translation.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.
ACM Trans. Program. Lang. Syst., 1997

From the guest editors.
Int. J. Parallel Program., 1997

Simulation/evaluation environment for a VLIW processor architecture.
IBM J. Res. Dev., 1997

Compilers for Instruction-Level Parallelism.
Computer, 1997

DAISY: Dynamic Compilation for 100% Architectural Compatibility.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Performance Analysis of Tree VLIW Architecture for Exploiting Branch ILP in Non-Numerical Code.
Proceedings of the 11th international conference on Supercomputing, 1997

1994
VLIW Compilation Techniques in a Superscalar Environment.
Proceedings of the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation (PLDI), 1994

1993
Making Compaction-Based Parallelization Affordable.
IEEE Trans. Parallel Distributed Syst., 1993

An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures.
Computer, 1993

A study on the number of memory ports in multiple instruction issue machines.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

On Performance, Efficiency of VLIW and Superscalar.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

An architectural framework for migration from CISC to higher performance platforms.
Proceedings of the 6th international conference on Supercomputing, 1992

1991
On Optimal Parallelization of Arbitrary Loops.
J. Parallel Distributed Comput., 1991

1990
A wide instruction word architecture for parallel execution of logic programs coded in BSL.
New Gener. Comput., 1990

An Expert System for Harmonizing Chorales in the Style of J. S. Bach.
J. Log. Program., 1990

Using a lookahead window in a compaction-based parallelizing compiler.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989
"Combining" as a compilation technique for VLIW architectures.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

On optimal loop parallelization.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

A global resource-constrained parallelization technique.
Proceedings of the 3rd international conference on Supercomputing, 1989

1987
A compilation technique for software pipelining of loops with conditional jumps.
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

An Efficient Logic Programming Language and Its Application to Music.
Proceedings of the Logic Programming, 1987

1986
An Expert System for Harmonizing Four-Part Chorales.
Proceedings of the 1986 International Computer Music Conference, 1986

An Expert System for Chorale Harmonization.
Proceedings of the 5th National Conference on Artificial Intelligence. Philadelphia, 1986

1984
An Expert System for Schenkerian Synthesis of Chorales in the Style of J. S. Bach.
Proceedings of the 1984 International Computer Music Conference, 1984

1980
Computer Counterpoint.
Proceedings of the 1980 International Computer Music Conference, 1980


  Loading...