Mary Jane Irwin

According to our database1, Mary Jane Irwin authored at least 336 papers between 1978 and 2016.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 1996, "For contributions to computer arithmetic, digital signal processing architectures, and electronic CAD and outstanding service to ACM/SIG activities.".

IEEE Fellow

IEEE Fellow 1994, "For contributions to computer arithmetic and digital signal processing architectures.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2016
Steven P. Levitan (1950-2016).
IEEE Design & Test, 2016

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.
ACM Trans. Design Autom. Electr. Syst., 2015

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
TACO, 2015

Platform-aware dynamic configuration support for efficient text processing on heterogeneous system.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

TaPEr: tackling power emergencies in the dark silicon era by exploiting resource scalability.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Design of energy-efficient circuits and systems using tunnel field effect transistors.
IET Circuits, Devices & Systems, 2013

Reshaping cache misses to improve row-buffer locality in multicore systems.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
REEact: a customizable virtual execution manager for multicore platforms.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012

Ultra Low Power Circuit Design Using Tunnel FETs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

An FPGA-based accelerator for cortical object classification.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A hybrid NoC design for cache coherence optimization for chip multiprocessors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Courteous cache sharing: being nice to others in capacity management.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Optimizing sensor movement planning for energy efficiency.
TOSN, 2011

Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Exploring heterogeneous NoC design space.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Total Power Optimization for Combinational Logic Using Genetic Algorithms.
Signal Processing Systems, 2010

On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Sec. Comput., 2010

On-chip memory space partitioning for chip multiprocessors using polyhedral algebra.
IET Computers & Digital Techniques, 2010

Technology scaling redirects main memories: technical perspective.
Commun. ACM, 2010

Cache topology aware computation mapping for multicores.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Compiler directed network-on-chip reliability enhancement for chip multiprocessors.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Shared caches in multicores: the good, the bad, and the ugly.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Dynamic core partitioning for energy efficiency.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Optimizing power and performance for reliable on-chip networks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Compiler-assisted soft error detection under performance and energy constraints in embedded systems.
ACM Trans. Embedded Comput. Syst., 2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.
IEEE Trans. Dependable Sec. Comput., 2009

Using Data Compression for Increasing Memory System Utilization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Process-Variation-Aware Adaptive Cache Architecture and Management.
IEEE Trans. Computers, 2009

Adapting application execution in CMPs using helper threads.
J. Parallel Distrib. Comput., 2009

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

In-Network Caching for Chip Multiprocessors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Arithmetic unit design using 180nm TSV-based 3D stacking technology.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Design Space Exploration for 3-D Cache.
IEEE Trans. VLSI Syst., 2008

Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Sec. Comput., 2008

Implementation and evaluation of a migration-based NUCA design for chip multiprocessors.
Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

A novel migration-based NUCA design for chip multiprocessors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Hierarchical Soft Error Estimation Tool (HSEET).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Managing power, performance and reliability trade-offs.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A helper thread based EDP reduction scheme for adapting application execution in CMPs.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Ring data location prediction scheme for Non-Uniform Cache Architectures.
Proceedings of the 26th International Conference on Computer Design, 2008

Integrated code and data placement in two-dimensional mesh based chip multiprocessors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A low-power phase change memory based hybrid cache architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Analysis and solutions to issue queue process variation.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Adaptive set pinning: managing shared caches in chip multiprocessors.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
Reducing non-deterministic loads in low-power caches via early cache set resolution.
Microprocessors and Microsystems, 2007

On-chip bus thermal analysis and optimisation.
IET Computers & Digital Techniques, 2007

Optimising power efficiency in trace cache fetch unit.
IET Computers & Digital Techniques, 2007

Evolving the ACM journal distribution program.
Commun. ACM, 2007

Architecting Microprocessor Components in 3D Design Space.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Impact of NBTI on FPGAs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Investigating Simple Low Latency Reliable Multiported Register Files.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Variation Impact on SER of Combinational Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variation Analysis of CAM Cells.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Phase-aware adaptive hardware selection for power-efficient scientific computations.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Memory Optimizations For Fast Power-Aware Sparse Computations.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Load Miss Prediction - Exploiting Power Performance Trade-offs.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Link Shutdown Opportunities During Collective Communications in 3-D Torus Nets.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Ring Prediction for Non-Uniform Cache Architectures.
Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007

2006
Block-based frequency scalable technique for efficient hierarchical coding.
IEEE Trans. Signal Processing, 2006

Reducing dynamic and leakage energy in VLIW architectures.
ACM Trans. Embedded Comput. Syst., 2006

Reducing code size through address register assignment.
ACM Trans. Embedded Comput. Syst., 2006

An efficient architecture for motion estimation and compensation in the transform domain.
IEEE Trans. Circuits Syst. Video Techn., 2006

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.
IEEE Trans. Circuits Syst. Video Techn., 2006

Plagiarism on the rise.
Commun. ACM, 2006

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Poster reception - Toward a power efficient computer architecture for Barnes-Hut N-body simulations.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Poster reception - Energy/performance modeling for collective communication in 3-D torus cluster networks.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Reducing NoC energy consumption through compiler-directed channel voltage scaling.
Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, 2006

Compiler-directed thermal management for VLIW functional units.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

A Parallel Architecture for Hardware Face Detection.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Conjugate gradient sparse solvers: performance-power characteristics.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

On improving performance and energy profiles of sparse scientific applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Enhancing L2 organization for CMPs with a center cell.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Characterizing the Performance and Energy Attributes of Scientific Simulations.
Proceedings of the Computational Science, 2006

On-chip bus thermal analysis and optimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Priority scheduling in digital microfluidics-based biochips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Activity clustering for leakage management in SPMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Object duplication for improving reliability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Compiler-guided leakage optimization for banked scratch-pad memories.
IEEE Trans. VLSI Syst., 2005

Soft errors issues in low-power caches.
IEEE Trans. VLSI Syst., 2005

Compiler-directed high-level energy estimation and optimization.
ACM Trans. Embedded Comput. Syst., 2005

Analyzing data reuse for cache reconfiguration.
ACM Trans. Embedded Comput. Syst., 2005

A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.
IEEE Trans. Computers, 2005

An integer linear programming-based tool for wireless sensor networks.
J. Parallel Distrib. Comput., 2005

Editorial.
JETC, 2005

Symmetric encryption in reconfigurable and custom hardware.
IJES, 2005

Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers, 2005

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.
Advances in Computers, 2005

Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Implementing LDPC Decoding on Network-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Nanosensor Array-Based VLSI Gas Discriminator.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Exploiting frequent field values in java objects for reducing heap memory requirements.
Proceedings of the 1st International Conference on Virtual Execution Environments, 2005

On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

High Performance Array Processor for Video Decoding.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Thermal-Aware Floorplanning Using Genetic Algorithms.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Optimizing sensor movement planning for energy efficiency.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Adaptive Software for Scientific Computing: Co-Managing Quality-Performance-Power Tradeoffs.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Exploiting Barriers to Optimize Power Consumption of CMPs.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Three-Dimensional Cache Design Exploration Using 3DCacti.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Using data compression in an MPSoC architecture for improving performance.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Leakage-Aware Interconnect for On-Chip Network.
Proceedings of the 2005 Design, 2005

BB-GC: Basic-Block Level Garbage Collection.
Proceedings of the 2005 Design, 2005

Thermal-Aware Task Allocation and Scheduling for Embedded Systems.
Proceedings of the 2005 Design, 2005

Compiler-Directed Instruction Duplication for Soft Error Detection.
Proceedings of the 2005 Design, 2005

Exploring technology alternatives for nano-scale FPGA interconnects.
Proceedings of the 42nd Design Automation Conference, 2005

Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Compiler-directed proactive power management for networks.
Proceedings of the 2005 International Conference on Compilers, 2005

Designing reliable circuit in the presence of soft errors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Customized on-chip memories for embedded chip multiprocessors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Compiler-directed selective data protection against soft errors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Instruction Scheduling for Low Power.
VLSI Signal Processing, 2004

Characterization and modeling of run-time techniques for leakage power reduction.
IEEE Trans. VLSI Syst., 2004

Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices.
IEEE Trans. Parallel Distrib. Syst., 2004

A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Reducing instruction cache energy consumption using a compiler-based strategy.
TACO, 2004

Optimizing Leakage Energy Consumption in Cache Bitlines.
Design Autom. for Emb. Sys., 2004

Embedded Hardware Face Detection.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An Architecture for Motion Estimation in the Transform Domain.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Designing Leakage Aware Multipliers.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

ChipPower: an architecture-level leakage simulator.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A generic reconfigurable neural network architecture as a network on chip.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Power-efficient implementation of turbo decoder in SDR system.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Code protection for resource-constrained embedded devices.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Field level analysis for heap space optimization in embedded java environments.
Proceedings of the 4th International Symposium on Memory Management, 2004

Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Fault Tolerant Algorithms for Network-On-Chip Interconnect.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

The Effect of Threshold Voltages on the Soft Error Rate.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Soft error and energy consumption interactions: a data cache perspective.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A Parallel Architecture for Secure FPGA Symmetric Encryption.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Improving soft-error tolerance of FPGA configuration bits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Banked scratch-pad memory management for reducing leakage energy consumption.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Analyzing software influences on substrate noise: an ADC perspective.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient VLSI implementation of inverse discrete cosine transform [image coding applications].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Exploring Wakeup-Free Instruction Scheduling.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Design of a nanosensor array architecture.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Tuning data replication for improving behavior of MPSoC applications.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A Dual-VDD Low Power FPGA Architecture.
Proceedings of the Field Programmable Logic and Application, 2004

Reducing leakage energy in FPGAs using region-constrained placement.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Exploring the Possibility of Operating in the Compressed Domain.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Using Data Compression to Increase Energy Savings in Multi-bank Memories.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

A Crosstalk Aware Interconnect with Variable Cycle Transmission.
Proceedings of the 2004 Design, 2004

Scheduling Reusable Instructions for Power Reduction.
Proceedings of the 2004 Design, 2004

Data compression for improving SPM behavior.
Proceedings of the 41th Design Automation Conference, 2004

Analyzing heap error behavior in embedded JVM environments.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Reliability-Aware Co-Synthesis for Embedded Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Partitioned instruction cache architecture for energy efficiency.
ACM Trans. Embedded Comput. Syst., 2003

Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.
IEEE Trans. Computers, 2003

Managing Leakage Energy in Cache Hierarchies.
J. Instruction-Level Parallelism, 2003

Power-Aware Designers at Odds with Power Grid Designers?
IEEE Design & Test of Computers, 2003

Leakage Current: Moore's Law Meets Static Power.
IEEE Computer, 2003

Analyzing Soft Errors in Leakage Optimized SRAM Design.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Effect of Power Optimizations on Soft Error Rate.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Heap compression for memory-constrained Java environments.
Proceedings of the 2003 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2003

Adapting instruction level parallelism for optimizing leakage in VLIW architectures.
Proceedings of the 2003 Conference on Languages, 2003

Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Interplay of energy and performance for disk arrays running transaction processing workloads.
Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

Energy optimization techniques in cluster interconnects.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Estimating influence of data layout optimizations on SDRAM energy consumption.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

On load latency in low-power caches.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Exploiting program hotspots and code sequentiality for instruction cache leakage management.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Computation and transmission energy modeling through profiling for MPEG4 video transmission.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Reducing dTLB Energy Through Dynamic Resizing.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Adapative Error Protection for Energy Efficiency.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Compiler Support for Reducing Leakage Energy Consumption.
Proceedings of the 2003 Design, 2003

Masking the Energy Behavior of DES Encryption.
Proceedings of the 2003 Design, 2003

Implications of technology scaling on leakage reduction techniques.
Proceedings of the 40th Design Automation Conference, 2003

VL-CDRAM: variable line sized cached DRAMs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Tracking object life cycle for leakage energy optimization.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Address Register Assignment for Reducing Code Size.
Proceedings of the Compiler Construction, 12th International Conference, 2003

Performance, energy, and reliability tradeoffs in replicating hot cache lines.
Proceedings of the International Conference on Compilers, 2003

Exploiting bank locality in multi-bank memories.
Proceedings of the International Conference on Compilers, 2003

2002
Energy-performance trade-offs for spatial access methods on memory-resident data.
VLDB J., 2002

A clock power model to evaluate impact of architectural and technology optimizations.
IEEE Trans. VLSI Syst., 2002

Tuning garbage collection for reducing memory system energy in an embedded java environment.
ACM Trans. Embedded Comput. Syst., 2002

Using Memory Compression for Energy Reduction in an Embedded Java System.
Journal of Circuits, Systems, and Computers, 2002

Evaluating Run-Time Techniques for Leakage Power Reduction.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Compiler-directed instruction cache leakage optimization.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-conscious compilation based on voltage scaling.
Proceedings of the 2002 Joint Conference on Languages, 2002

Compiler-directed cache polymorphism.
Proceedings of the 2002 Joint Conference on Languages, 2002

Adaptive Garbage Collection for Battery-Operated Environments.
Proceedings of the 2nd Java Virtual Machine Research and Technology Symposium, 2002

Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Impact of Technology Scaling in the Clock System Power.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Designing Energy-Efficient Software.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter.
Proceedings of the IEEE International Conference on Acoustics, 2002

Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Tuning Garbage Collection in an Embedded Java Environment.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

EAC: A Compiler Framework for High-Level Energy Estimation and Optimization.
Proceedings of the 2002 Design, 2002

Power-Efficient Trace Caches.
Proceedings of the 2002 Design, 2002

A Complete Phase-Locked Loop Power Consumption Model.
Proceedings of the 2002 Design, 2002

Scheduler-based DRAM energy management.
Proceedings of the 39th Design Automation Conference, 2002

Energy savings through compression in embedded Java environments.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Leakage Energy Management in Cache Hierarchies.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations.
VLSI Design, 2001

Design considerations for databus charge recovery.
IEEE Trans. VLSI Syst., 2001

Architecture-level power estimation and design experiments.
ACM Trans. Design Autom. Electr. Syst., 2001

Hardware and Software Techniques for Controlling DRAM Power Modes.
IEEE Trans. Computers, 2001

Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Analyzing energy behavior of spatial access methods for memory-resident data.
Proceedings of the VLDB 2001, 2001

vEC: virtual energy counters.
Proceedings of the 2001 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis For Software Tools and Engineering, 2001

SoC Design Skills: Collaboration Builds a Stronger SoC Design Team.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Morphable Cache Architectures: Potential Benefits.
Proceedings of The Workshop on Languages, 2001

Energy Behavior of Java Applications from the Memory Perspective.
Proceedings of the 1st Java Virtual Machine Research and Technology Symposium, 2001

Power-aware partitioned cache architectures.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Influence of Array Allocation Mechanisms on Memory System Energy.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Use of Local Memory for Efficient Java Execution.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Framework for Energy Estimation of VLIW Architecture.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

DRAM Energy Management Using Software and Hardware Directed Power Mode Control.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Dynamic Management of Scratch-Pad Memory Space.
Proceedings of the 38th Design Automation Conference, 2001

Energy-efficient instruction cache using page-based placement.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
The design of the MGAP-2: a micro-grained massively parallel array.
IEEE Trans. VLSI Syst., 2000

Editorial.
ACM Trans. Design Autom. Electr. Syst., 2000

A Holistic Approach to System Level Energy Optimization.
Proceedings of the Integrated Circuit Design, 2000

Towards Energy-Aware Iteration Space Tiling.
Proceedings of the Languages, 2000

Experimental Evaluation of Energy Behavior of Iteration Space Tiling.
Proceedings of the Languages and Compilers for Parallel Computing, 2000

Memory system energy (poster session): influence of hardware-software optimizations.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Energy-driven integrated hardware-software optimizations using SimplePower.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Hardware/Software Co-design for Real-Time Physical Modeling.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

Energy-Aware Instruction Scheduling.
Proceedings of the High Performance Computing, 2000

A comparative study of power efficient SRAM designs.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

SPARTA: Simulation of Physics on a Real-Time Architecture.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

The design and use of simplepower: a cycle-accurate energy estimation tool.
Proceedings of the 37th Conference on Design Automation, 2000

Influence of compiler optimizations on system power.
Proceedings of the 37th Conference on Design Automation, 2000

Energy-oriented compiler optimizations for partitioned memory architectures.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Aggressive Dynamic Execution of Decoded Traces.
VLSI Signal Processing, 1999

A Fast and Simple Steiner Routing Heuristic.
Discrete Applied Mathematics, 1999

Databus charge recovery: practical considerations.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

The Design of a Register Renaming Unit.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Editorial Message.
VLSI Signal Processing, 1998

A Parallel ASIC Architecture for Efficient Fractal Image Coding.
VLSI Signal Processing, 1998

The logarithmic number system for strength reduction in adaptive filtering.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Aggressive Dynamic Execution of Multimedia Kernel Traces.
IPPS/SPDP, 1998

Number representations for reducing switched capacitance in subband coding.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Validation of an Architectural Level Power Analysis Technique.
Proceedings of the 35th Conference on Design Automation, 1998

1997
A fast algorithm for minimizing the Elmore delay to identified critical sinks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Motion Analysis on the Micro Grained Array Processor.
Real-Time Imaging, 1997

Power-Area Trade-Offs in Divided Word Line Memory Arrays.
Journal of Circuits, Systems, and Computers, 1997

A Simulation Methodology for Software Energy Evaluation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Techniques for low energy software.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

An extended addressing mode for low power.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Mixed-autonomy local interconnect for reconfigurable SIMD arrays.
Proceedings of the Fourth International on High-Performance Computing, 1997

A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

The MGAP Family of Processor Arrays.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996
An optimal time multiplication free algorithm for edge detection on a mesh.
VLSI Signal Processing, 1996

Transistor sizing for low power CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Design tradeoffs in high speed multipliers and FIR filters.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Power comparisons for barrel shifters.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Design tradeoffs in CMOS FIR filters.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Instruction level power profiling.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Some Issues in Gray Code Addressing.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Recent Developments in Performance Driven Steiner Routing: An Overview.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Energy Characterization based on Clustering.
Proceedings of the 33st Conference on Design Automation, 1996

An Architectural Design For Parallel Fractal Compression.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Digit pipelined arithmetic on fine-grain array processors.
VLSI Signal Processing, 1995

Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A simulation methodology for evaluating parallel computers.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Unifying carry-sum and signed-digital number representations for low power.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

High-throughput and low-power DSP using clocked-CMOS circuitry.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

The MGAP-2: an advanced, massively parallel VLSI signal processor.
Proceedings of the 1995 International Conference on Acoustics, 1995

Fast algorithm for performance-oriented Steiner routing.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Accurate Estimation of Combinational Circuit Activity.
Proceedings of the 32st Conference on Design Automation, 1995

Motion Estimation Algorithms on Fine Grain Array Processor.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

The MGAP's programming environment and the *C++ language.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Reducing the number of counters needed for integer multiplication.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
Power-delay characteristics of CMOS adders.
IEEE Trans. VLSI Syst., 1994

Logic synthesis for field-programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

An edge-based heuristic for Steiner routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Polynomial Time Testability of Circuits Generated by Input Decomposition.
IEEE Trans. Computers, 1994

Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
IEEE Trans. Computers, 1994

Dynamic Space Warping Algorithms on Fine-Graln Array Processors.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

Digit pipelined discrete wavelet transform.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

FPGA-based synthesis of FSMs through decomposition.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

A SIMD solution to the sequence comparison problem on the MGAP.
Proceedings of the International Conference on Application Specific Array Processors, 1994

Rapid prototyping with programmable control paths.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. VLSI Syst., 1993

A Massively Parallel, Micro-Grained VLSI Architecture.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Image Processing with the MGAP: A Cost Effective Solution.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

Multi-way FSM decomposition based on interconnect complexity.
Proceedings of the European Design Automation Conference 1993, 1993

A new optimization driven clustering algorithm for large circuits.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Efficiently computing communication complexity for multilevel logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

ELM-A Fast Addition Algorithm Discovered by a Program.
IEEE Trans. Computers, 1992

Intermediate-level vision tasks on a memory array architecture.
Mach. Vis. Appl., 1992

ECube: An Efficient Architecture for Analyzing Time-Varying Spectra.
Proceedings of the Fifth International Conference on VLSI Design, 1992

PERFLEX: a performance driven module generator.
Proceedings of the conference on European design automation, 1992

Experiments with a Performance Driven Module Generator.
Proceedings of the 29th Design Automation Conference, 1992

1991
Image processing on a memory array architecture.
VLSI Signal Processing, 1991

A Two-Dimensional, Distributed Logic Architecture.
IEEE Trans. Computers, 1991

Digit Serial Multipliers.
J. Parallel Distrib. Comput., 1991

1990
A case for digit serial VLSI signal processors.
VLSI Signal Processing, 1990

Exploiting communication complexity for multilevel logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

Being Stingy with Multipliers.
IEEE Trans. Computers, 1990

An integrated, multi-level synthesis system.
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

Test generation in circuits constructed by input decomposition.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Logic synthesis for programmable logic devices.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Distributed Fault Diagnosis in the Butterfly Parallel Processor.
Proceedings of the International Conference on Parallel Processing, 1989

A Comparison of Four Two-dimensional Gate Matrix Layout Tools.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Multi-Level Logic Synthesis Using Communication Complexity.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
A digit pipelined dynamic time warp processor [word recognition].
IEEE Trans. Acoustics, Speech, and Signal Processing, 1988

Special Issue on Parallelism in Computer Arithmetic.
J. Parallel Distrib. Comput., 1988

DECOMPOSER: A Synthesizer for Systolic Systems.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Digit pipelined processors.
The Journal of Supercomputing, 1987

Fast Methods for Switch-Level Verification of MOS Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

The Arithmetic Cube.
IEEE Trans. Computers, 1987

Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial.
IEEE Computer, 1987

An Overview of the Penn State Design System.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

Regular Area-Time Efficient Carry-Lookahead Adders.
J. Parallel Distrib. Comput., 1986

1985
Regular, area-time efficient carry-lookahead adders.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983
Fully Digit On-Line Networks.
IEEE Trans. Computers, 1983

Numerical limitations on the design of digit online networks.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1982
A digit online arithmetic simulator.
Proceedings of the International Conference on Parallel Processing, 1982

1981
A rational arithmetic processor.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

1980
Online Pipeline Systems for Recursive Numeric Computations.
Proceedings of the 7th Annual Symposium on Computer Architecture, 1980

1979
On-Line Algorithms for the Design of Pipeline Architectures.
Proceedings of the 6th Annual Symposium on Computer Architecture, 1979

1978
A Pipelined Processing Unit for On-Line Division.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

Reconfigurable Pipeline Systems.
Proceedings of the Proceedings 1978 ACM Annual Conference, 1978


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