Shekhar Srikantaiah

According to our database1, Shekhar Srikantaiah authored at least 22 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Design of a Host Interface Logic for GC-Free SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2014
HIOS: A host interface I/O scheduler for Solid State Disks.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2012
Courteous cache sharing: being nice to others in capacity management.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PEPON: performance-aware hierarchical power budgeting for NoC based multicores.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
METE: meeting end-to-end QoS in multicores through system-wide resource management.
Proceedings of the SIGMETRICS 2011, 2011

QoS aware storage cache management in multi-server environments.
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011

Feedback control based cache reliability enhancement for emerging multicores.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Improving shared cache behavior of multithreaded object-oriented applications in multicores.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Adaptive QoS Decomposition and Control for Storage Cache Management in Multi-server Environments.
Proceedings of the 11th IEEE/ACM International Symposium on Cluster, 2011

2010
Coordinated power management of voltage islands in CMPs.
Proceedings of the SIGMETRICS 2010, 2010

CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors.
Proceedings of the Conference on High Performance Computing Networking, 2010

Cache topology aware computation mapping for multicores.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Adaptive multi-level cache allocation in distributed storage architectures.
Proceedings of the 24th International Conference on Supercomputing, 2010

SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

2009
A case for integrated processor-cache partitioning in chip multiprocessors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Dynamic storage cache allocation in multi-server architectures.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

SHARP control: controlled shared cache management in chip multiprocessors.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008
SPM management using Markov chain based data access prediction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Integrated code and data placement in two-dimensional mesh based chip multiprocessors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Adaptive set pinning: managing shared caches in chip multiprocessors.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008


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