Ettore Amirante

According to our database1, Ettore Amirante authored at least 9 papers between 2001 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2009
Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2005
Power-Clock Gating in Adiabatic Logic Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Energieoptimierung durch Adiabatische Schaltungstechnik.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Impact of process parameter variations on the energy dissipation in adiabatic logic.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
Power Supply Net for Adiabatic Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

2003
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.
Proceedings of the Integrated Circuit and System Design, 2003

An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment.
Proceedings of the ESSCIRC 2003, 2003

2001
Three-dimensional Statistical Modeling of the Effects of the Random Distribution of Dopants in Deep Sub-micron nMOSFETs.
VLSI Design, 2001


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