Christoph Heer

According to our database1, Christoph Heer authored at least 20 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
The Metop-Sg Sca wind Scatterometer: Cdr Development Status and Performance Overview.
Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

2018
In-Flight Calibration of the Metop-Sg Sca Wind Scatterometer.
Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

The Biomass SAR Instrument: Development Status and Performance Overview.
Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

2016
Verification of scan-on-receive beamforming for X-Band HRWS applications.
Proceedings of the 2016 IEEE International Geoscience and Remote Sensing Symposium, 2016

2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
Int. J. Embed. Real Time Commun. Syst., 2012

Exploring pausible clocking based GALS design for 40-nm system integration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2004
A scalable compact architecture for the computation of integer binary logarithms through linear approximation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Extremely Low-Power Logic.
Proceedings of the 2004 Design, 2004

Ultra-Low-Power Design: Device and Logic Design Approaches.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.
Proceedings of the Integrated Circuit and System Design, 2003

Investigations on a new high resolution wide swath SAR concept.
Proceedings of the 2003 IEEE International Geoscience and Remote Sensing Symposium, 2003

An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment.
Proceedings of the ESSCIRC 2003, 2003

2002
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing.
J. VLSI Signal Process., 2002

2001
Self-routing crossbar switch with internal contention resolution.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Coprocessor architecture for MPEG-4 video object rendering.
Proceedings of the Visual Communications and Image Processing 2000, 2000

Co-processor architecture for MPEG-4 main profile visual compositing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Architecture of an Image Rendering Co-Processor for MPEG-4 Systems.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999
Design and architecture of the MPEG-4 video rendering co-processor 'TANGRAM'.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1995
Entwurfsmethode für selbstgetaktete VLSI-Datenpfadarchitekturen.
PhD thesis, 1995


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