Giuseppe Iannaccone

Orcid: 0000-0003-3375-1647

  • University of Pisa, Italy

According to our database1, Giuseppe Iannaccone authored at least 58 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.


IEEE Fellow

IEEE Fellow 2015, "For contributions to modeling transport and noise processes in nanoelectronic devices".



In proceedings 
PhD thesis 


Online presence:



Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C.
IEEE Access, 2024

IEEE Access, 2024

Electromagnetic Design of an Inductive Wireless Power Transfer System for Endoscopic Capsule.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2023

A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion.
CoRR, 2022

All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification.
IEEE Access, 2022

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS.
IEEE Access, 2022

A 6.78 MHz Maximum Efficiency Tracking Active Rectifier with Load Modulation Control for Wireless Power Transfer to Implantable Medical Devices.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Integrating Mobile IoT Devices into the Arrowhead Framework Using Web of Things.
Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022

Power Electronics Based on Wide-Bandgap Semiconductors: Opportunities and Challenges.
IEEE Access, 2021

Electric-field controlled spin transport in bilayer CrI3.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits.
IEEE Access, 2020

Stability and Startup of Non Linear Loop Circuits.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Variability-aware design of a bandgap voltage reference with 0.18% standard deviation and 68 nW power consumption.
Int. J. Circuit Theory Appl., 2018

A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018

Design of a 3T current reference for low-voltage, low-power operation.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Charge Injection in Normally-Off p-GaN Gate AlGaN/GaN-on-Si HFETs.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

An Ultralow-Voltage Energy-Efficient Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Low energy/delay overhead level shifter for wide-range voltage conversion.
Int. J. Circuit Theory Appl., 2017

A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvesting.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A Sub-kT/q Voltage Reference Operating at 150 mV.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Last-Meter Smart Grid Embedded in an Internet-of-Things Platform.
IEEE Trans. Smart Grid, 2015

A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity.
Int. J. Circuit Theory Appl., 2015

Internet-of-things infrastructure as a platform for distributed measurement applications.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014

A picopower temperature-compensated, subthreshold CMOS voltage reference.
Int. J. Circuit Theory Appl., 2014

Multiscale Modeling for Graphene-Based Nanoscale Transistors.
Proc. IEEE, 2013

Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models.
Microelectron. J., 2013

A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation.
Proceedings of the Design, Automation and Test in Europe, 2013

An intragrid implementation embedded in an Internet of Things platform.
Proceedings of the IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2013

Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability.
IEEE J. Solid State Circuits, 2011

A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference.
IEEE J. Solid State Circuits, 2011

An energy case for hybrid datacenters.
ACM SIGOPS Oper. Syst. Rev., 2010

Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Noise and reliability in simulated thin metal films.
Microelectron. Reliab., 2008

Low-voltage nanopower clock generator for RFID applications.
Microelectron. J., 2008

CMOS unclonable system for secure authentication based on device variability.
Proceedings of the ESSCIRC 2008, 2008

A Sub-1-V, 10 ppm/°C, Nanopower Voltage Reference Generator.
IEEE J. Solid State Circuits, 2007

Equivalent resistance and noise of cascaded mesoscopic cavities.
Int. J. Circuit Theory Appl., 2007

A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low-Voltage Low-Power CMOS Oscillator with Low Temperature and Process Sensitivity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process Variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Ultra-low-power temperature compensated voltage reference generator.
Microelectron. J., 2006

Ultra-low power PSK backscatter modulator for UHF and microwave RFID transponders.
Microelectron. J., 2006

Ultra-low-power flash memory in standard 0.35µm CMOS for passive microwave RFID transponders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Perspectives and challenges in nanoscale device modeling.
Microelectron. J., 2005

Ultra low power RF section of a passive microwave RFID transponder in 0.35µm BiCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An ultra-low-power, temperature compensated voltage reference generator.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Extraction of the trap distribution responsible for SILCs in MOS structures from the measurements and simulations of DC and noise properties.
Microelectron. Reliab., 2004

Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.
Proceedings of the Integrated Circuit and System Design, 2003

Simulation of failure time distributions of metal lines under electromigration.
Microelectron. Reliab., 2002

Program, Erase and Retention Times of Thin-oxide Flash-EEPROMs.
VLSI Design, 2001

Detection of Quantum Cellular Automaton Action in Silicon-on-insulator Cells.
VLSI Design, 2001

Three-dimensional Statistical Modeling of the Effects of the Random Distribution of Dopants in Deep Sub-micron nMOSFETs.
VLSI Design, 2001

Semiclassical simulation of quantum cellular automaton circuits.
Int. J. Circuit Theory Appl., 2001

Modeling of Shot Noise in Resonant Tunneling Structures.
VLSI Design, 1998