Giuseppe Iannaccone
Orcid: 0000-0003-3375-1647Affiliations:
- University of Pisa, Italy
According to our database1,
Giuseppe Iannaccone
authored at least 57 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to modeling transport and noise processes in nanoelectronic devices".
Timeline
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Online presence:
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Bibliography
2024
2023
Electromagnetic Design of an Inductive Wireless Power Transfer System for Endoscopic Capsule.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2023
2022
A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion.
CoRR, 2022
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification.
IEEE Access, 2022
Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS.
IEEE Access, 2022
A 6.78 MHz Maximum Efficiency Tracking Active Rectifier with Load Modulation Control for Wireless Power Transfer to Implantable Medical Devices.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022
2021
Power Electronics Based on Wide-Bandgap Semiconductors: Opportunities and Challenges.
IEEE Access, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the Device Research Conference, 2021
2020
Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits.
IEEE Access, 2020
2019
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2018
Variability-aware design of a bandgap voltage reference with 0.18% standard deviation and 68 nW power consumption.
Int. J. Circuit Theory Appl., 2018
A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Int. J. Circuit Theory Appl., 2017
A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvesting.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Smart Grid, 2015
A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity.
Int. J. Circuit Theory Appl., 2015
Internet-of-things infrastructure as a platform for distributed measurement applications.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015
2014
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014
Int. J. Circuit Theory Appl., 2014
2013
Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models.
Microelectron. J., 2013
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2013
2012
Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Sensitivity-based investigation of threshold voltage variability in 32-nm flash memory cells.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
2010
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
2008
Proceedings of the ESSCIRC 2008, 2008
2007
IEEE J. Solid State Circuits, 2007
Int. J. Circuit Theory Appl., 2007
A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process Variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Microelectron. J., 2006
Microelectron. J., 2006
Ultra-low-power flash memory in standard 0.35µm CMOS for passive microwave RFID transponders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Extraction of the trap distribution responsible for SILCs in MOS structures from the measurements and simulations of DC and noise properties.
Microelectron. Reliab., 2004
2003
Proceedings of the Integrated Circuit and System Design, 2003
2002
Microelectron. Reliab., 2002
2001
VLSI Design, 2001
Three-dimensional Statistical Modeling of the Effects of the Random Distribution of Dopants in Deep Sub-micron nMOSFETs.
VLSI Design, 2001
Int. J. Circuit Theory Appl., 2001
1998