Eugene Koskin

Orcid: 0000-0002-4253-0312

According to our database1, Eugene Koskin authored at least 19 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Quantum Theory and Application of Contextual Optimal Transport.
CoRR, 2024

Gate-Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms.
CoRR, 2024

2023
An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

2021
Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Electrostatic Control and Entanglement of CMOS Position-Based Qubits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Simulation Methodology for Electron Transfer in CMOS Quantum Dots.
Proceedings of the Computational Science - ICCS 2020, 2020

Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis.
Proceedings of the European Conference on Circuit Theory and Design, 2020

FPGA Validation of Event-Driven ADPLL.
Proceedings of the European Conference on Circuit Theory and Design, 2020

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays.
IEEE Access, 2018

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Mode-locking in a network of kuramoto-like oscillators.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015


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