Eldar Zianbetov

According to our database, Eldar Zianbetov authored at least 17 papers between 2011 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A comprehensive in-depth study of tri-state inverter based DCO.

Mehdi Terosiet, Eldar Zianbetov, Farouk Vallette, Marie-Minerve Louërat, Patrick Garda, Dimitri Galayko, Sylvain Feruglio

Microelectron. J., 2020

2019

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.

Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2016

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks.

Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs.

Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Radiative Effects on MRAM-Based Non-Volatile Elementary Structures.

Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing.

Edith Beigné, Jean-Frédéric Christmann, Eldar Zianbetov, Gregory di Pendina

Proceedings of the European Conference on Circuit Theory and Design, 2015

Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology.

Eldar Zianbetov, Edith Beigné, Gregory di Pendina

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014

A reconfigurable distributed architecture for clock generation in large many-core SoC.

Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

"Swimming pool"-like distributed architecture for clock generation in large many-core SoC.

Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Complexity in heterogeneous systems on chips: Dsign and analysis challenges.

Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Distributed clock generator for synchronous SoC using ADPLL network.

Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation.

Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

All-digital PLL array provides reliable distributed clock for SOCs.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops.

Jean-Michel Akre, Jérôme Juillard, Mohammad Javidan, Eldar Zianbetov, Dimitri Galayko, Anton Korniienko, Éric Colinet

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011