Chuan Shan

According to our database, Chuan Shan authored at least 12 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.

Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2016

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks.

Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs.

Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014

Distributed clock generator for globally and locally synchronous chips with a large size. (Générateur distribué d'horloge pour puces globalement et localement synchrones de grande taille).

Chuan Shan

PhD thesis, 2014

A reconfigurable distributed architecture for clock generation in large many-core SoC.

Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

"Swimming pool"-like distributed architecture for clock generation in large many-core SoC.

Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.

Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell

Microelectron. J., 2013

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

On-chip clock error characterization for clock distribution system.

Chuan Shan, Dimitri Galayko, François Anceau

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Distributed clock generator for synchronous SoC using ADPLL network.

Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Design and Modeling of ADPLL with sliding-window for wide range frequency tracking.

Chuan Shan, Dimitri Galayko, François Anceau

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011