Fahong Zhang

According to our database, Fahong Zhang authored at least 12 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

STEED: Space and Time-Efficient Encrypted Database Using FHE.

Fahong Zhang, Zhen Gu, Yiran Li, Yilei Wang, Cheng Hong, Zhaohui Chen, Yufei Wang, Yanheng Lu, Meng Li, Leibo Liu, Sheng Wang, Feifei Li, Chen Yang, Dimin Niu, Yuan Xie

IEEE Trans. Dependable Secur. Comput., 2026

2025

An Efficient Polynomial Multiplication Accelerator for Lattice-Based Cryptography With a 2-D Winograd-Based Divide-and-Conquer Method.

Jianfei Wang, Zhen Zhou, Fahong Zhang, Yishuo Meng, Jia Hou, Xin Tang, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., December, 2025

PBSAcc: A High-Performance Hardware Accelerator for FHE With Improved Batch Programmable Bootstrapping.

Jianfei Wang, Fahong Zhang, Zhen Zhou, Yishuo Meng, Jia Hou, Xin Tang, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline.

Jia Hou, Jianfei Wang, Yishuo Meng, Fahong Zhang, Yang Su, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme.

Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption.

Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm.

Fahong Zhang, Chen Yang, Rui Zong, Xinran Zheng, Jianfei Wang, Yishuo Meng

IEEE Trans. Inf. Forensics Secur., 2024

2023

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su

IEEE Trans. Very Large Scale Integr. Syst., August, 2023