Mieszko Lis

According to our database1, Mieszko Lis authored at least 37 papers between 2005 and 2023.

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Bibliography

2023
ViaLin: Path-Aware Dynamic Taint Analysis for Android.
Proceedings of the 31st ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering, 2023

Sunstone: A Scalable and Versatile Scheduler for Mapping Tensor Algebra on Spatial Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

HuffDuff: Stealing Pruned DNNs from Sparse Accelerators.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2021
Slicer4J: a dynamic slicer for Java.
Proceedings of the ESEC/FSE '21: 29th ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering, 2021

Mandoline: Dynamic Slicing of Android Applications with Trace-Based Alias Analysis.
Proceedings of the 14th IEEE Conference on Software Testing, Verification and Validation, 2021

Accelerating DNNs inference with predictive layer fusion.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

CHOPIN: Scalable Graphics Rendering in Multi-GPU Systems via Parallel Image Composition.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

A Case for Emerging Memories in DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Turbo Maximum-a-Posteriori Equalizer for Faster-than-Nyquist Applications.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2DCC: Cache Compression in Two Dimensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Thesaurus: Efficient Cache Compression via Dynamic Clustering.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Full Deep Neural Network Training On A Pruned Weight Budget.
Proceedings of Machine Learning and Systems 2019, 2019

A unifying abstraction for data structure splicing.
Proceedings of the International Symposium on Memory Systems, 2019

2018
DropBack: Continuous Pruning During Training.
CoRR, 2018

High-Performance GPU Transactional Memory via Eager Conflict Detection.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Gaussian mixture error estimation for approximate circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2015
The Execution Migration Machine: Directoryless Shared-Memory Architecture.
Computer, 2015

2014
Hardware-level fine-grained thread migration.
PhD thesis, 2014

Thread Migration Prediction for Distributed Shared Caches.
IEEE Comput. Archit. Lett., 2014

2013
Optimal and Heuristic Application-Aware Oblivious Routing.
IEEE Trans. Computers, 2013

Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Hardware-level thread migration in a 110-core shared-memory multiprocessor.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012
HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
DCC: A Dependable Cache Coherence Multicore Architecture.
IEEE Comput. Archit. Lett., 2011

A method for probing the mutational landscape of amyloid structure.
Bioinform., 2011

Brief announcement: distributed shared memory based on computation migration.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Deadlock-free fine-grained thread migration.
Proceedings of the NOCS 2011, 2011

Scalable, accurate multicore simulation in the 1000-core era.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Memory coherence in the age of multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2009
Efficient stochastic simulation of reaction-diffusion processes via direct compilation.
Bioinform., 2009

Static virtual channel allocation in oblivious routing.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Path-based, randomized, oblivious, minimal routing.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.
Proceedings of the PACT 2009, 2009

2005
Synthesis of synchronous assertions with guarded atomic actions.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005


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