Fatemeh Refan

According to our database1, Fatemeh Refan authored at least 10 papers between 2007 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
Signature oriented model pruning to facilitate multi-threaded processors debugging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2011
NoC simulation modeling in DEVS-suite.
Proceedings of the 2011 Spring Simulation Multi-conference, 2011

2009
A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages.
Proceedings of the IEEE International Conference on Acoustics, 2009

2008
"Plug & Test" at System Level via Testable TLM Primitives.
Proceedings of the 2008 IEEE International Test Conference, 2008

Reliability in Application Specific Mesh-Based NoC Architectures.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

2007
Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform.
Proceedings of the International Conference on Image Processing, 2007

A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform.
Proceedings of the IEEE International Conference on Acoustics, 2007


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