Paolo Prinetto

According to our database1, Paolo Prinetto authored at least 242 papers between 1979 and 2019.

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Bibliography

2019
Design and Review of Water Management System Using Ethernet, Wi-Fi 802.11n, Modbus, and Other Communication Standards.
Wireless Personal Communications, 2019

Challenges and Solutions in Emerging Memory Testing.
IEEE Trans. Emerging Topics Comput., 2019

CFI: Control Flow Integrity or Control Flow Interruption?
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2018
An abstraction layer enabling pervasive hardware-reconfigurable systems.
IJES, 2018

2017
Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

An object-oriented open software architecture for security applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Side-channel analysis of SEcube™ platform.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Scan chain encryption for the test, diagnosis and debug of secure circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Standards-based tools and services for building lifelong learning pathways.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

Holistic security via complex HW/SW platforms.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
JETC, 2016

Security primitives (PUF and TRNG) with STT-MRAM.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

SEcube™: An open-source security platform in a single SoC.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Towards a highly reliable SRAM-based PUFs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications.
IEEE Trans. VLSI Syst., 2015

SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs.
TRETS, 2015

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embedded Comput. Syst., 2015

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Usability of Online Assistance From Semiliterate Users' Perspective.
Int. J. Hum. Comput. Interaction, 2015

STT-MRAM-Based Strong PUF Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Power-aware voltage tuning for STT-MRAM reliability.
Proceedings of the 20th IEEE European Test Symposium, 2015

STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

DTIS 2015 foreword.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Online self adjusting progressive age monitoring of timing variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

STT MRAM-Based PUFs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
TACO, 2014

Integrating MultiWordNet with Italian Sign Language lexical resources.
Expert Syst. Appl., 2014

A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris.
EURASIP J. Adv. Sig. Proc., 2014

A novel methodology to increase fault tolerance in autonomous FPGA-based systems.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Integration of STT-MRAM model into CACTI simulator.
Proceedings of the 9th International Design and Test Symposium, 2014

On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial).
Proceedings of the 19th IEEE European Test Symposium, 2014

DTIS 2014 foreword.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ABLUR: An FPGA-based adaptive deblurring core for real-time applications.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Design and optimization of adaptable BCH codecs for NAND flash memories.
Microprocess. Microsystems, 2013

Exploring a New Dimension in Code Mobility for Ubiquitous Embedded Systems.
Proceedings of the 2013 IEEE 10th International Conference on Ubiquitous Intelligence and Computing and 2013 IEEE 10th International Conference on Autonomic and Trusted Computing, 2013

Fault mitigation strategies for CUDA GPUs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Ef3S: An evaluation framework for flash-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Increasing the robustness of CUDA Fermi GPU-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications.
Proceedings of the 8th International Design and Test Symposium, 2013

ZipStream: Improving dependability in dynamic partial reconfiguration.
Proceedings of the 8th International Design and Test Symposium, 2013

FEMIP: A high performance FPGA-based features extractor & matcher for space applications.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A software-based self test of CUDA Fermi GPUs.
Proceedings of the 18th IEEE European Test Symposium, 2013

Stereo vision system for capture and removal of space debris.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

AIDI: An adaptive image denoising FPGA-based IP-core for real-time applications.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
A platform-independent user-friendly dictionary from Italian to LIS.
Proceedings of the Eighth International Conference on Language Resources and Evaluation, 2012

Efficient system-level aging prediction.
Proceedings of the 17th IEEE European Test Symposium, 2012

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Software-Based Self-Test of Set-Associative Cache Memories.
IEEE Trans. Computers, 2011

Efficient multi-level fault simulation of HW/SW systems for structural faults.
SCIENCE CHINA Information Sciences, 2011

An area-efficient 2-D convolution implementation on FPGA for space applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Validation & Verification of an EDA automated synthesis tool.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A unifying formalism to support automated synthesis of SBSTs for embedded caches.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Genetic Defect Based March Test Generation for SRAM.
Proceedings of the Applications of Evolutionary Computation, 2011

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Improving accessibility for deaf people: an editor for computer assisted translation through virtual avatars.
Proceedings of the 13th International ACM SIGACCESS Conference on Computers and Accessibility, 2011

2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

A Web Based Platform for Sign Language Corpus Creation.
Proceedings of the Computers Helping People with Special Needs, 2010

Automated synthesis of EDACs for FLASH memories with user-selectable correction capability.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Sign Language synthesis using hand motion acquisition.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Communication interface synthesis from TLM 2.0 to RTL.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

EDACs and test integration strategies for NAND flash memories.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Exploring modeling and testing of NAND flash memories.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Facilitating testability of TLM FIFO: SystemC implementations.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Microprocessor fault-tolerance via on-the-fly partial reconfiguration.
Proceedings of the 15th European Test Symposium, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Are IEEE-1500-Compliant Cores Really Compliant to the Standard?.
IEEE Design & Test of Computers, 2009

Designing health care applications for the deaf.
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009

Test infrastructures evaluation at transaction level.
Proceedings of the 2009 IEEE International Test Conference, 2009

FLARE: A design environment for FLASH-based space applications.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

System Level Testing via TLM 2.0 Debug Transport Interface.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Test exploration and validation using transaction level models.
Proceedings of the Design, Automation and Test in Europe, 2009

A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
IEEE Standard 1500 Compliance Verification for Embedded Cores.
IEEE Trans. VLSI Syst., 2008

March Test Generation Revealed.
IEEE Trans. Computers, 2008

"Plug & Test" at System Level via Testable TLM Primitives.
Proceedings of the 2008 IEEE International Test Conference, 2008

Reliability in Application Specific Mesh-Based NoC Architectures.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Automating defects simulation and fault modeling for SRAMs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Functional testing approaches for "BIFST-able" tlm_fifo.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

Applying March Tests to K-Way Set-Associative Cache Memories.
Proceedings of the 13th European Test Symposium, 2008

An Avatar-Based Italian Sign Language Visualization System.
Proceedings of the Electronic Healthcare, First International Conference, 2008

Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.
IET Computers & Digital Techniques, 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Automating the IEEE std.1500 compliance verification for embedded cores.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006
A Wiki for discussing and promoting best practices in research.
Commun. ACM, 2006

Single-Event Upset Analysis and Protection in High Speed Circuits.
Proceedings of the 11th European Test Symposium, 2006

A 22n March Test for Realistic Static Linked Faults in SRAMs.
Proceedings of the 11th European Test Symposium, 2006

Automatic March Tests Generation for Multi-Port SRAMs.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic march tests generations for static linked faults in SRAMs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
System-level functional testing from UML specifications in end-of-production industrial environments.
STTT, 2005

Agent-based test and repair of distributed systems.
J. Embedded Computing, 2005

A Dependable Autonomic Computing Environment for Self-Testing of Complex Heterogeneous Systems.
Electron. Notes Theor. Comput. Sci., 2005

Reconfigurable systems self-healing using mobile hardware agents.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

March AB, March AB1: new March tests for unlinked dynamic memory faults.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Automatic March tests generation for static and dynamic faults in SRAMs.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

2004
Test Technology Technical Council Newsletter.
J. Electronic Testing, 2004

Test Technology TC Newsletter.
IEEE Design & Test of Computers, 2004

Towards Microagent based DBIST/DBISR.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003
Design for Testability for Highly Reconfigurable Component-Based Systems.
Electron. Notes Theor. Comput. Sci., 2003

A Hierarchical Infrastructure for SoC Test Management.
IEEE Design & Test of Computers, 2003

Online Self-Repair of FIR Filters.
IEEE Design & Test of Computers, 2003

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.
IEEE Communications Magazine, 2003

Designing and Testing High Dependable Memories for Aerospace Applications.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Test Engineering Education in Europe: the EuNICE-Test Project.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Agent Based DBIST/DBISR And Its Web/Wireless Management.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Data Critically Estimation In Software Applications.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAUST: FAUlt-injection Script-based Tool.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Watchdog Processor to Detect Data and Control Flow Errors.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
An on-line BIST RAM architecture with self-repair capabilities.
IEEE Trans. Reliability, 2002

Initializability analysis of synchronous sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 2002

DFT and BIST of a Multichip Module for High-Energy Physics Experiments.
IEEE Design & Test of Computers, 2002

Static Analysis of SEU Effects on Software Applications.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Efficient Design of System Test: A Layered Architecture.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

An Optimal Algorithm for the Automatic Generation of March Tests.
Proceedings of the 2002 Design, 2002

Beyond UML to an End-of-Line Functional Test Engine.
Proceedings of the 2002 Design, 2002

Specification and Design of a New Memory Fault Simulator.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
A Self-Repairing Execution Unit for Microprogrammed Processors.
IEEE Micro, 2001

Guest Editorial.
J. Electronic Testing, 2001

Online and Offline BIST in IP-Core Design.
IEEE Design & Test of Computers, 2001

GRAAL: a tool for highly dependable SRAMs generation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Towards a unified test process: from UML to end-of-line functional test.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Validation of a Software Dependability Tool via Fault Injection Experiments.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Embedded tutorial: TRP: integrating embedded test and ATE.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

On applying the set covering model to reseeding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

SEU effect analysis in an open-source router via a distributed fault injection environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Control-Flow Checking via Regular Expressions.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Memory Read Faults: Taxonomy and Automatic Test Generation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.
J. Electronic Testing, 2000

Non-intrusive BIST for systems-on-a-chip.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A software development kit for dependable applications in embedded systems.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A programmable BIST architecture for clusters of multiple-port SRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A Family of Self-Repair SRAM Cores.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A C/C++ Source-to-Source Compiler for Dependable Applications.
Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Self-Repairing in a Micro-Programmed Processor for Dependable Applications.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

'BOND': An Interposition Agents Based Fault Injector for Windows NT.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Optimal Hardware Pattern Generation for Functional BIST.
Proceedings of the 2000 Design, 2000

1999
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Exploiting Behavioral Information in Gate-Level ATPG.
J. Electronic Testing, 1999

Testing embedded memories in telecommunication systems.
IEEE Communications Magazine, 1999

RT-level TPG Exploiting High-Level Synthesis Information.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

An on-line BISTed SRAM IP core.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Testing an MCM for high-energy physics experiments: a case study.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
EXFI: a low-cost fault injection system for embedded microprocessor-based boards.
ACM Trans. Design Autom. Electr. Syst., 1998

The General Product Machine: a New Model for Symbolic FSM Traversal.
Formal Methods in System Design, 1998

Integrating Online and Offline Testing of a Switching Memory.
IEEE Design & Test of Computers, 1998

A Test Pattern Generation Methodology for Low-Power Consumption.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A fault injection environment for microprocessor-based boards.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
Proceedings of the 1998 Design, 1998

Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.
Proceedings of the 1998 Design, 1998

A Test Pattern Generation Algorithm Exploiting Behavioral Information.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Cellular automata for deterministic sequential test pattern generation.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Hardware Test: Can We Learn from Software Testing?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

Testability Analysis and ATPG on Behavioral RT-Level VHDL.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997

A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

New static compaction techniques of test sequences for sequential circuits.
Proceedings of the European Design and Test Conference, 1997

Hybrid symbolic-explicit techniques for the graph coloring problem.
Proceedings of the European Design and Test Conference, 1997

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
Proceedings of the European Design and Test Conference, 1997

Simulation-based verification of network protocols performance.
Proceedings of the Advances in Hardware Design and Verification, 1997

Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Guaranteeing Testability in Re-encoding for Low Power.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Circular Self-Test Path for FSMs.
IEEE Design & Test of Computers, 1996

Scan insertion criteria for low design impact.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
Proceedings of the Parallel Problem Solving from Nature, 1996

Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits.
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996

A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
Proceedings of the High-Performance Computing and Networking, 1996

Fault tolerant and BIST design of a FIFO cell.
Proceedings of the conference on European design automation, 1996

Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.
Proceedings of the conference on European design automation, 1996

On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996

Advanced Techniques for GA-based sequential ATPGs.
Proceedings of the 1996 European Design and Test Conference, 1996

Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Industrial BIST of Embedded RAMs.
IEEE Design & Test of Computers, 1995

A portable ATPG tool for parallel and distributed systems.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Improving topological ATPG with symbolic techniques.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Testing a Switching Memory in a Telcommunication System.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A PVM tool for automatic test generation on parallel and distributed systems.
Proceedings of the High-Performance Computing and Networking, 1995

GARDA: a diagnostic ATPG for large synchronous sequential circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

Using symbolic techniques to find the maximum clique in very large sparse graphs.
Proceedings of the 1995 European Design and Test Conference, 1995

Proving testing preorders for process algebra descriptions.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
An industrial experience in the built-in self test of embedded RAMs.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A new functional fault model for system-level descriptions.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Making the Circular Self-Test Path Technique Effective for Real Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994

An experimental analysis of the effectiveness of the circular self-test path technique.
Proceedings of the Proceedings EURO-DAC'94, 1994

System-Level Modeling and Verification: a Comprehensive Design Methodology.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A process algebra interpretation of a verification oriented overlanguage of VHDL.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
An approach to sequential circuit diagnosis based on formal verification techniques.
J. Electronic Testing, 1993

An efficient tool for system-level verification of behaviors and temporal properties.
Proceedings of the European Design Automation Conference 1993, 1993

Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

A Methodology for System-Level Design for Verifiability.
Proceedings of the Correct Hardware Design and Verification Methods, 1993

1992
Sequential Circuit Diagnosis Based on Formal Verification Techniques.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Cross-fertilizing FSM verification techniques and sequential diagnosis.
Proceedings of the conference on European design automation, 1992

A New Model for Improving symbolic Product Machine Traversal.
Proceedings of the 29th Design Automation Conference, 1992

1991
TPDL: Extended Temporal Profile Description Language.
Softw., Pract. Exper., 1991

Proving finite state machines correct with an automaton-based method.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

Resolution-based correctness proofs of synchronous circuits.
Proceedings of the conference on European design automation, 1991

1990
Exact probabilistic testability measures for multi-output circuits.
J. Electronic Testing, 1990

A diagnostic test pattern generation algorithm.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Diagnosis oriented test pattern generation.
Proceedings of the European Design Automation Conference, 1990

Model Checking and Graph Theory in Sequential ATPG.
Proceedings of the Computer-Aided Verification, 1990

The Use of Model Checking in ATPG for Sequential Circuits.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989
Knowledge-based systems as an aid to computer-aided repair.
Microprocess. Microsystems, 1989

Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988
ESTA: an expert system for DFT rule verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Formal Verification of Hardware Correctness: Introduction and Survey of Current Research.
IEEE Computer, 1988

1986
Experiences in Prolog-Based DFT Rule Checking.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1985
Testing Strategy and Technique for Macro-Based Circuits.
IEEE Trans. Computers, 1985

1984
PART: Programmable Array Testing Based on a Partitioning Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1984

1983
A Hierarchical Description Model for Microcode.
IEEE Trans. Computers, 1983

A review of fault models for lsi/vlsi devices.
Software & Microsystems, 1983

A new integrated system for PLA testing and verification.
Proceedings of the 20th Design Automation Conference, 1983

1982
A Machine-independent Approach to Microprogram Synthesis.
Softw., Pract. Exper., 1982

Microcode compaction via microblock definition.
Proceedings of the 15th annual workshop on Microprogramming, 1982

1979
Design and implementation of a flexible and interactive microprogram simulator.
Proceedings of the 12th annual workshop on Microprogramming, 1979


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