Feifei Niu
Orcid: 0000-0002-4123-4554
According to our database1,
Feifei Niu
authored at least 21 papers
between 2011 and 2025.
Collaborative distances:
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Bibliography
2025
ACM Comput. Surv., November, 2025
Differential privacy-enabled federated learning for secure neural synchronization in protecting industrial data streams.
Clust. Comput., September, 2025
CoRR, August, 2025
Refactoring ≠ Bug-Inducing: Improving Defect Prediction with Code Change Tactics Analysis.
CoRR, July, 2025
Enhancement Report Approval Prediction: A Comparative Study of Large Language Models.
CoRR, June, 2025
Towards Understanding Bugs in Distributed Training and Inference Frameworks for Large Language Models.
CoRR, June, 2025
CoRR, May, 2025
Assessing and Advancing Benchmarks for Evaluating Large Language Models in Software Engineering Tasks.
CoRR, May, 2025
TVR: Automotive System Requirement Traceability Validation and Recovery Through Retrieval-Augmented Generation.
CoRR, April, 2025
2024
Empir. Softw. Eng., November, 2024
What Makes a High-Quality Training Dataset for Large Language Models: A Practitioners' Perspective.
Proceedings of the 39th IEEE/ACM International Conference on Automated Software Engineering, 2024
Proceedings of the 2024 IEEE/ACM 46th International Conference on Software Engineering: Companion Proceedings, 2024
2023
Proceedings of the 20th IEEE/ACM International Conference on Mining Software Repositories, 2023
Proceedings of the 45th IEEE/ACM International Conference on Software Engineering, 2023
2022
IEEE Trans. Serv. Comput., 2022
IEEE Trans. Instrum. Meas., 2022
Proceedings of the Internetware 2022: 13th Asia-Pacific Symposium on Internetware, Hohhot, China, June 11, 2022
2021
Cloud Technology Dual Data Center Information System Based on Disaster Recovery Platform.
Proceedings of the 2021 International Conference on Machine Learning and Big Data Analytics for IoT Security and Privacy, 2021
2015
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2011
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011