Jianlei Yang

According to our database, Jianlei Yang authored at least 72 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.

Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

2023

IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.

Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.

Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao

Sci. China Inf. Sci., April, 2023

TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices.

Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao

CoRR, 2023

Architectural Implications of GNN Aggregation Programming Abstractions.

Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu

CoRR, 2023

Lossy and Lossless (L²) Post-training Model Size Compression.

Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms.

Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM.

Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.

Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

S² Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.

Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao

IEEE Trans. Computers, 2022

Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao

IEEE Trans. Computers, 2022

Exploring the Factors of Students' Online Learning Based On Structural Equation Modeling.

Han Wan, Hongzhen Luo, Zihao Zhong, Jianlei Yang

Proceedings of the IEEE International Conference on Teaching, 2022

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.

Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.

Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao

IEEE Trans. Neural Networks Learn. Syst., 2021

Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution.

Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.

Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao

CoRR, 2021

RoSearch: Search for Robust Student Architectures When Distilling Pre-trained Language Models.

Xin Guo, Jianlei Yang, Haoyi Zhou, Xucheng Ye, Jianxin Li

CoRR, 2021

Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.

Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu

CoRR, 2021

Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.

Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu

Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021

FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update.

Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao

Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021

2020

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.

Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.

Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing.

Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao

ACM J. Emerg. Technol. Comput. Syst., 2020

Prototyping federated learning on edge computing systems.

Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao

Frontiers Comput. Sci., 2020

TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations.

Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang

CoRR, 2020

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.

Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao

CCF Trans. High Perform. Comput., 2020

TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations.

Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang

Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method.

Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Dual-Plane Switch Architecture for Time-Triggered Ethernet.

Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures.

Jianlei Yang, Xiaopeng Gao, Weisheng Zhao

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Accelerating CNN Training by Pruning Activation Gradients.

Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen

Proceedings of the Computer Vision - ECCV 2020, 2020

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.

Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.

Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment.

Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang

Sustain. Comput. Informatics Syst., 2019

ELFISH: Resource-Aware Federated Learning on Heterogeneous Edge Devices.

Zirui Xu, Zhao Yang, Jinjun Xiong, Jianlei Yang, Xiang Chen

CoRR, 2019

Accelerating CNN Training by Sparsifying Activation Gradients.

Xucheng Ye, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao

CoRR, 2019

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.

Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing.

Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface.

Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform.

Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.

Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng

J. Comput. Sci. Technol., 2018

A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.

Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao

Proceedings of the International Conference on Field-Programmable Technology, 2018

A Novel Approach on Entity Linking for Encyclopedia Infoboxes.

Xufeng Li, Jianlei Yang, Richong Zhang, Hongyuan Ma

Proceedings of the Knowledge Graph and Semantic Computing. Knowledge Computing and Language Understanding, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.

Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment.

Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang

Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Generative adversarial network based scalable on-chip noise sensor placement.

Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.

Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.

Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.

Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao

IEEE Trans. Very Large Scale Integr. Syst., 2016

Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.

Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao

IEEE Trans. Reliab., 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.

Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Spintronic Memristor as Interface Between DNA and Solid State Devices.

Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A novel circuit design of true random number generator using magnetic tunnel junction.

You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy.

Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY.

Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.

Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification.

Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao

IEEE Trans. Very Large Scale Integr. Syst., 2015

An overview on memristor crossabr based neuromorphic circuit and architecture.

Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback.

Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Early stage real-time SoC power estimation using RTL instrumentation.

Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

PowerRush: An Efficient Simulator for Static Power Grid Analysis.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2014

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis.

Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi

IEEE Trans. Very Large Scale Integr. Syst., 2014

Power supply noise aware evaluation framework for side channel attacks and countermeasures.

Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Fast vectorless power grid verification using maximum voltage drop location estimation.

Wei Zhao, Yici Cai, Jianlei Yang

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Selected inversion for vectorless power grid verification by exploiting locality.

Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification.

Wei Zhao, Yici Cai, Jianlei Yang

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

PowerRush : Efficient transient simulation for power grid analysis.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

PowerRush: A linear simulator for power grid.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast poisson solver preconditioned method for robust power grid analysis.

Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011