Yici Cai

According to our database1, Yici Cai authored at least 232 papers between 1999 and 2018.

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Bibliography

2018
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Spear and Shield: Evolution of Integrated Circuit Camouflaging.
J. Comput. Sci. Technol., 2018

Look at Boundary: A Boundary-Aware Face Alignment Algorithm.
CoRR, 2018

Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks.
Proceedings of the 2018 International Conference on Computing, 2018

Electromagnetic equalizer: an active countermeasure against EM side-channel attack.
Proceedings of the International Conference on Computer-Aided Design, 2018

Electromigration Design Rule aware Global and Detailed Routing Algorithm.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Look at Boundary: A Boundary-Aware Face Alignment Algorithm.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

ASAX: Automatic security assertion extraction for detecting Hardware Trojans.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

HLIFT: A high-level information flow tracking method for detecting hardware Trojans.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2017

An Effective Power Grid Optimization Approach for the Electromigration Reliability.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Cell spreading optimization for force-directed global placers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

TeenRead: An Adolescents Reading Recommendation System Towards Online Bibliotherapy.
Proceedings of the 2017 IEEE International Congress on Big Data, 2017

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Is the Secure IC camouflaging really secure?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient framework for configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Control-fluidic CoDesign for paper-based digital microfluidic biochips.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Sequence-pair-based placement and routing for flow-based microfluidic biochips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification.
IEEE Trans. VLSI Syst., 2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. VLSI Syst., 2015

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.
J. Comput. Sci. Technol., 2015

Register Clustering Methodology for Low Power Clock Tree Synthesis.
J. Comput. Sci. Technol., 2015

SIAR: Customized real-time interactive router for analog circuits.
Integration, 2015

Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips.
IEEE Design & Test, 2015

Fast synthesis of low power clock trees based on register clustering.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Early stage real-time SoC power estimation using RTL instrumentation.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
PowerRush: An Efficient Simulator for Static Power Grid Analysis.
IEEE Trans. VLSI Syst., 2014

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis.
IEEE Trans. VLSI Syst., 2014

Length matching in detailed routing for analog and mixed signal circuits.
Microelectronics Journal, 2014

Trusted Integrated Circuits: The Problem and Challenges.
J. Comput. Sci. Technol., 2014

Fast and scalable parallel layout decomposition in double patterning lithography.
Integration, 2014

RSMT construction algorithm based on Congestion-Oriented Flexibility.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

A register clustering algorithm for low power clock tree synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Accurate prediction of detailed routing congestion using supervised data learning.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

MCFRoute: a detailed router based on multi-commodity flow method.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Power supply noise aware evaluation framework for side channel attacks and countermeasures.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Fast vectorless power grid verification using maximum voltage drop location estimation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Time-domain performance bound analysis for analog and interconnect circuits considering process variations.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

VFGR: A very fast parallel global router with accurate congestion modeling.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.
Integration, 2013

SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Selected inversion for vectorless power grid verification by exploiting locality.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Performance bound and yield analysis for analog circuits under process variations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A new splitting graph construction algorithm for SIAR router.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Analog routing considering min-area constraint.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A DyadicCluster method used for nonlinear placement.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

PowerRush : Efficient transient simulation for power grid analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs.
IEEE Trans. VLSI Syst., 2011

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A novel fine-grain track routing approach for routability and crosstalk optimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical full-chip dynamic power estimation considering spatial correlations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

PowerRush: A linear simulator for power grid.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast poisson solver preconditioned method for robust power grid analysis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

SIAR: splitting-graph-based interactive analog router.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A fast recursive detailed routing algorithm for hierarchical FPGAs.
Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011

2010
ECP- and CMP-Aware Detailed Routing Algorithm for DFM.
IEEE Trans. VLSI Syst., 2010

Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method.
IEEE Trans. VLSI Syst., 2010

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.
IEEE Trans. VLSI Syst., 2010

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Integration, 2010

Optimization of via distribution and stacked via in multi-layered P/G networks.
Integration, 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Analog circuit shielding routing algorithm based on net classification.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Scaling power/ground solvers on multi-core with memory bandwidth awareness.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.
Proceedings of the Design, Automation and Test in Europe, 2010

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.
Proceedings of the 2010 14th International Conference on Computer Supported Cooperative Work in Design, 2010

Efficient model reduction of interconnects via double gramians approximation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Efficient power grid integrity analysis using on-the-fly error check and reduction.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
An MTCMOS technology for low-power physical design.
Integration, 2009

A single layer zero skew clock routing in X architecture.
Science in China Series F: Information Sciences, 2009

Cell shifting aware of wirelength and overlap.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Decoupling capacitance efficient placement for reducing transient power supply noise.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fast congestion-aware timing-driven placement for island FPGA.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

An efficient decoupling capacitance optimization using piecewise polynomial models.
Proceedings of the Design, Automation and Test in Europe, 2009

GPU friendly fast Poisson solver for structured power grid network analysis.
Proceedings of the 46th Design Automation Conference, 2009

A thermal-driven force-directed floorplanning algorithm for 3D ICs.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Fast placement for large-scale hierarchical FPGAs.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.
IEEE Trans. on Circuits and Systems, 2008

Random Walk Guided Decap Embedding for Power/Ground Network Optimization.
IEEE Trans. on Circuits and Systems, 2008

Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration, 2008

Large scale P/G grid transient simulation using hierarchical relaxed approach.
Integration, 2008

Efficient range pattern matching algorithm for process-hotspot detection.
IET Circuits, Devices & Systems, 2008

Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.
IEICE Transactions, 2008

Low Power Gated Clock Tree Driven Placement.
IEICE Transactions, 2008

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.
IEICE Transactions, 2008

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.
IEICE Transactions, 2008

Application of optical proximity correction technology.
Science in China Series F: Information Sciences, 2008

Full-chip routing system for reducing Cu CMP & ECP variation.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

DFM Based Detailed Routing Algorithm for ECP and CMP.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Leakage power optimization for clock network using dual-Vth technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Gate planning during placement for gated clock network.
Proceedings of the 26th International Conference on Computer Design, 2008

A novel performance driven power gating based on distributed sleep transistor network.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
Proceedings of the FPL 2008, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Heuristic power/ground network and floorplan co-design method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Vertical via design techniques for multi-layered P/G networks.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Wire density driven top-down global placement for CMP variation control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Yield-Driven Gridless Router.
J. Comput. Sci. Technol., 2007

An efficient quadratic placement based on search space traversing technology.
Integration, 2007

Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
Integration, 2007

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.
IEICE Transactions, 2007

Voltage Island Generation in Cell Based Dual-Vdd Design.
IEICE Transactions, 2007

CMP-aware Maze Routing Algorithm for Yield Enhancement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Power Delivery Aware Floorplanning for Voltage Island Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Effective Acceleration of Iterative Slack Distribution Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

New timing and routability driven placement algorithms for FPGA synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Physical aware clock skew rescheduling.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Dummy fill aware buffer insertion during routing.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Statistical model order reduction for interconnect circuits considering spatial correlations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Logic and Layout Aware Voltage Island Generation for Low Power Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Legitimate Skew Clock Routing with Buffer Insertion.
VLSI Signal Processing, 2006

Multilevel Routing With Redundant Via Insertion.
IEEE Trans. on Circuits and Systems, 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. on Circuits and Systems, 2006

Power/Ground Network Optimization Considering Decap Leakage Currents.
IEEE Trans. on Circuits and Systems, 2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment.
IEEE Trans. on Circuits and Systems, 2006

Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Priority-Based Routing Resource Assignment Considering Crosstalk.
J. Comput. Sci. Technol., 2006

Time-domain analysis methodology for large-scale RLC circuits and its applications.
Science in China Series F: Information Sciences, 2006

Clock Skew Scheduling Under Process Variations.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

High accurate pattern based precondition method for extremely large power/ground grid analysis.
Proceedings of the 2006 International Symposium on Physical Design, 2006

A novel low-power physical design methodology for MTCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Congestion-driven W-shape multilevel full-chip routing framework.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Performance and power aware buffered tree construction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High performance clock routing in X-architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient process-hotspot detection using range pattern matching.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Efficient early stage resonance estimation techniques for C4 package.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

DFM-aware Routing for Yield Enhancement.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Crosstalk-Aware Routing Resource Assignment.
J. Comput. Sci. Technol., 2005

Shielding Area Optimization Under the Solution of Interconnect Crosstalk.
J. Comput. Sci. Technol., 2005

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.
J. Comput. Sci. Technol., 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.
IEICE Transactions, 2005

Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions, 2005

Crosstalk and Congestion Driven Layer Assignment Algorithm.
IEICE Transactions, 2005

Reliable buffered clock tree routing algorithm with process variation tolerance.
Science in China Series F: Information Sciences, 2005

A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Efficient Simulation of Power/Ground Networks with Package and Vias.
Proceedings of the Integrated Circuit and System Design, 2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.
Proceedings of the Integrated Circuit and System Design, 2005

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Zero skew clock routing with tree topology construction using simulated annealing method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A global interconnect optimization algorithm under accurate delay model using solution space smoothing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Integrated routing resource assignment for RLC crosstalk minimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

Improved multilevel routing with redundant via placement for yield and reliability.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new algorithm for layout of dark field alternating phase shifting masks.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Partitioning-based approach to fast on-chip decap budgeting and minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Analysis of buffered hybrid structured clock networks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

VLSI on-chip power/ground network optimization considering decap leakage currents.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Relaxed hierarchical power/ground grid analysis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst., 2004

Corner block list representation and its application to floorplan optimization.
IEEE Trans. on Circuits and Systems, 2004

Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Corner block list representation and its application with boundary constraints.
Science in China Series F: Information Sciences, 2004

A buffer planning algorithm for chip-level floorplanning.
Science in China Series F: Information Sciences, 2004

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Proceedings of the Integrated Circuit and System Design, 2004

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Quick and effective buffered legitimate skew clock routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk driven routing resource assignment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Algorithm for yield driven correction of layout.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Layer assignment algorithm for RLC crosstalk minimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Buffer allocation algorithm with consideration of routing congestion.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
FaSa: A Fast and Stable Quadratic Placement Algorithm.
J. Comput. Sci. Technol., 2003

An efficient hierarchical timing-driven Steiner tree algorithm for global routing.
Integration, 2003

An integrated floorplanning with an efficient buffer planning algorithm.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining clustering and partitioning in quadratic placement.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
Proceedings of the 40th Design Automation Conference, 2003

A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A path-based timing-driven quadratic placement algorithm.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol., 2002

A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior.
Science in China Series F: Information Sciences, 2002

An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Floorplanning with abutment constraints based on corner block list.
Integration, 2001

Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
Proceedings of the 38th Design Automation Conference, 2001

VLSI floorplanning with boundary constraints based on corner block list.
Proceedings of ASP-DAC 2001, 2001

A new congestion-driven placement algorithm based on cell inflation.
Proceedings of ASP-DAC 2001, 2001

2000
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

MMP: a novel placement algorithm for combined macro block and standard cell layout design.
Proceedings of ASP-DAC 2000, 2000

Area routing oriented hierarchical corner stitching with partial bin.
Proceedings of ASP-DAC 2000, 2000

1999
A Timing-Driven Block Placer Based on Sequence Pair Model.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A New Global Routing Algorithm Independent Of Net Ordering.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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