Qiang Zhou

According to our database, Qiang Zhou authored at least 165 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.

Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Static Probability Analysis Guided RTL Hardware Trojan Test Generation.

Haoyi Wang, Qiang Zhou, Yici Cai

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

A survey on machine learning-based routing for VLSI physical design.

Lin Li, Yici Cai, Qiang Zhou

Integr., 2022

Intelligent and kernelized placement: A survey.

Rui Hao, Yici Cai, Qiang Zhou

Integr., 2022

MimCo: Masked Image Modeling Pre-training with Contrastive Teacher.

Qiang Zhou, Chaohui Yu, Hao Luo, Zhibin Wang, Hao Li

CoRR, 2022

Point RCNN: An Angle-Free Framework for Rotated Object Detection.

Qiang Zhou, Chaohui Yu, Zhibin Wang, Hao Li

CoRR, 2022

TransMarker: A Pure Vision Transformer for Facial Landmark Detection.

Wenyan Wu, Yici Cai, Qiang Zhou

Proceedings of the 26th International Conference on Pattern Recognition, 2022

A circuit protection method based on minterm perturbation.

Shiling Luo, Wenchao Gao, Le Huang, Qiang Zhou

Proceedings of the 18th International Conference on Computational Intelligence and Security, 2022

2021

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits.

Jianwang Zhai, Yici Cai, Qiang Zhou

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks.

Jing Wang, Yici Cai, Qiang Zhou

J. Comput. Sci. Technol., 2021

Object Detection Made Simpler by Eliminating Heuristic NMS.

Qiang Zhou, Chaohui Yu, Chunhua Shen, Zhibin Wang, Hao Li

CoRR, 2021

A game theory approach for RTL security verification resources allocation.

Haoyi Wang, Yici Cai, Qiang Zhou

CCF Trans. High Perform. Comput., 2021

A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model.

Jing Wang, Yici Cai, Qiang Zhou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network.

Lin Li, Yici Cai, Qiang Zhou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Multiple Features Driven Author Name Disambiguation.

Qiang Zhou, Wei Chen, Weiqing Wang, Jiajie Xu, Lei Zhao

Proceedings of the 2021 IEEE International Conference on Web Services, 2021

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.

Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data.

Wenyan Wu, Yici Cai, Qiang Zhou

Proceedings of the 16th IEEE International Conference on Automatic Face and Gesture Recognition, 2021

Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework.

Qiang Zhou, Chaohui Yu, Zhibin Wang, Qi Qian, Hao Li

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

2020

TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting.

Zhuoqian Yang, Wentao Zhu, Wayne Wu, Chen Qian, Qiang Zhou, Bolei Zhou, Chen Change Loy

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.

Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods.

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding.

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

Integr., 2019

A high-level information flow tracking method for detecting information leakage.

Haoyi Wang, Chenguang Wang, Yici Cai, Qiang Zhou

Integr., 2019

Deep coupling neural network for robust facial landmark detection.

Wenyan Wu, Xingzhe Wu, Yici Cai, Qiang Zhou

Comput. Graph., 2019

Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks.

Jing Wang, Yici Cai, Ming Yan, Qiang Zhou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

FAB: A Robust Facial Landmark Detection Framework for Motion-Blurred Videos.

Keqiang Sun, Wayne Wu, Tinghao Liu, Shuo Yang, Quan Wang, Qiang Zhou, Zuochang Ye, Chen Qian

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

2018

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.

Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Spear and Shield: Evolution of Integrated Circuit Camouflaging.

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

J. Comput. Sci. Technol., 2018

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit.

Shan Jiang, Ning Xu, Xueyan Wang, Qiang Zhou

J. Comput. Sci. Technol., 2018

Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks.

Jia Wei, Qiang Zhou, Yici Cai

Proceedings of the 2018 International Conference on Computing, 2018

Electromagnetic equalizer: an active countermeasure against EM side-channel attack.

Chenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou

Proceedings of the International Conference on Computer-Aided Design, 2018

Electromigration Design Rule aware Global and Detailed Routing Algorithm.

Xiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Look at Boundary: A Boundary-Aware Face Alignment Algorithm.

Wayne Wu, Chen Qian, Shuo Yang, Quan Wang, Yici Cai, Qiang Zhou

Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks.

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

ASAX: Automatic security assertion extraction for detecting Hardware Trojans.

Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

HLIFT: A high-level information flow tracking method for detecting hardware Trojans.

Chenguang Wang, Yici Cai, Qiang Zhou

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Effective Power Grid Optimization Approach for the Electromigration Reliability.

Ming Yan, Yici Cai, Chenguang Wang, Qiang Zhou

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Crossover Ring Oscillator PUF.

Zihan Pang, Jiliang Zhang, Qiang Zhou, Shuqian Gong, Xu Qian, Bin Tang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Cell spreading optimization for force-directed global placers.

Xueyan Wang, Yici Cai, Qiang Zhou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.

Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.

Chenguang Wang, Yici Cai, Qiang Zhou

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack.

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function.

Jiliang Zhang, Qiang Wu, Yipeng Ding, Yong-Qiang Lv, Qiang Zhou, Zhihua Xia, Xingming Sun, Xing-Wei Wang

J. Comput. Sci. Technol., 2016

Is the Secure IC camouflaging really secure?

Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient framework for configurable RO PUF.

Zhuwei Chen, Yici Cai, Qiang Zhou, Gang Qu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.

Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.

Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification.

Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao

IEEE Trans. Very Large Scale Integr. Syst., 2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.

Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze

IEEE Trans. Very Large Scale Integr. Syst., 2015

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.

Zhongdong Qi, Yici Cai, Qiang Zhou

J. Comput. Sci. Technol., 2015

Register Clustering Methodology for Low Power Clock Tree Synthesis.

Chao Deng, Yici Cai, Qiang Zhou

J. Comput. Sci. Technol., 2015

SIAR: Customized real-time interactive router for analog circuits.

Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham

Integr., 2015

Fast synthesis of low power clock trees based on register clustering.

Chao Deng, Yici Cai, Qiang Zhou

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators.

Mingze Gao, Khai Lai, Jiliang Zhang, Gang Qu, Aijiao Cui, Qiang Zhou

Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014

PowerRush: An Efficient Simulator for Static Power Grid Analysis.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2014

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis.

Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi

IEEE Trans. Very Large Scale Integr. Syst., 2014

Length matching in detailed routing for analog and mixed signal circuits.

Hailong Yao, Qiang Gao, Yici Cai, Qiang Zhou, Chiu-Wing Sham

Microelectron. J., 2014

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs.

Jiliang Zhang, Gang Qu, Yong-Qiang Lv, Qiang Zhou

J. Comput. Sci. Technol., 2014

Trusted Integrated Circuits: The Problem and Challenges.

Yong-Qiang Lv, Qiang Zhou, Yici Cai, Gang Qu

J. Comput. Sci. Technol., 2014

RSMT construction algorithm based on Congestion-Oriented Flexibility.

Ziyang Qi, Kun Ma, Qiang Zhou, Yici Cai

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

A register clustering algorithm for low power clock tree synthesis.

Chao Deng, Yici Cai, Qiang Zhou

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Accurate prediction of detailed routing congestion using supervised data learning.

Zhongdong Qi, Yici Cai, Qiang Zhou

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

MCFRoute: a detailed router based on multi-commodity flow method.

Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Power supply noise aware evaluation framework for side channel attacks and countermeasures.

Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

VFGR: A very fast parallel global router with accurate congestion modeling.

Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.

Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang

Integr., 2013

Selected inversion for vectorless power grid verification by exploiting locality.

Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.

Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.

Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Design and implementation of a group-based RO PUF.

Chi-En Daniel Yin, Gang Qu, Qiang Zhou

Proceedings of the Design, Automation and Test in Europe, 2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection.

Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, Gang Qu

Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.

Zhongdong Qi, Yici Cai, Qiang Zhou

Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

A new splitting graph construction algorithm for SIAR router.

Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Analog routing considering min-area constraint.

Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

TimFastPlace: Critical-path based timing driven FastPlace.

Jiliang Zhang, Yongqiang Lu, Qiang Zhou, Qiang Wu, Yaping Lin, Kang Zhao

IEICE Electron. Express, 2012

A DyadicCluster method used for nonlinear placement.

Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

PowerRush : Efficient transient simulation for power grid analysis.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.

Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs.

Qiang Zhou, Jin Shi, Bin Liu, Yici Cai

IEEE Trans. Very Large Scale Integr. Syst., 2011

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.

Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A novel fine-grain track routing approach for routability and crosstalk optimization.

Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.

Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

PowerRush: A linear simulator for power grid.

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast poisson solver preconditioned method for robust power grid analysis.

Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

SIAR: splitting-graph-based interactive analog router.

Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A fast recursive detailed routing algorithm for hierarchical FPGAs.

Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai

Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011

A timing-perspective study on the wire model in placement.

Liu Liu, Yongqiang Lu, Qiang Zhou

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

ECP- and CMP-Aware Detailed Routing Algorithm for DFM.

Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong

IEEE Trans. Very Large Scale Integr. Syst., 2010

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement.

Hui Dai, Qiang Zhou, Jinian Bian

J. Comput. Sci. Technol., 2010

Thermal Impacts of Leakage Power in 2D/3D floorplanning.

Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong

J. Circuits Syst. Comput., 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.

Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A low power clock network placement framework.

Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Peak current reduction by simultaneous state replication and re-encoding.

Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Behavioral level dual-vth design for reduced leakage power with thermal awareness.

Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian

Proceedings of the Design, Automation and Test in Europe, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.

Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu

Proceedings of the Design, Automation and Test in Europe, 2010

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.

Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian

Proceedings of the 2010 14th International Conference on Computer Supported Cooperative Work in Design, 2010

2009

An MTCMOS technology for low-power physical design.

Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong

Integr., 2009

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach.

Haixia Yan, Qiang Zhou, Xianlong Hong

Integr., 2009

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.

Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Cell shifting aware of wirelength and overlap.

Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Decoupling capacitance efficient placement for reducing transient power supply noise.

Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fast congestion-aware timing-driven placement for island FPGA.

Jinpeng Zhao, Qiang Zhou, Yici Cai

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Improve clock gating through power-optimal enable function selection.

Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Information hiding for trusted system design.

Junjun Gu, Gang Qu, Qiang Zhou

Proceedings of the 46th Design Automation Conference, 2009

Global density smoothing technique for analytical placement algorithm.

Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

A thermal-driven force-directed floorplanning algorithm for 3D ICs.

Yun Huang, Qiang Zhou, Yici Cai, Haixia Yan

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Fast placement for large-scale hierarchical FPGAs.

Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong

Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.

Junbo Yu, Qiang Zhou, Jinian Bian

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.

Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Application of optical proximity correction technology.

Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang

Sci. China Ser. F Inf. Sci., 2008

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.

Haixia Yan, Qiang Zhou, Xianlong Hong

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

DFM Based Detailed Routing Algorithm for ECP and CMP.

Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A novel performance driven power gating based on distributed sleep transistor network.

Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.

Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong

Proceedings of the FPL 2008, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.

Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Wire density driven top-down global placement for CMP variation control.

Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Yield-Driven Gridless Router.

Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong

J. Comput. Sci. Technol., 2007

An efficient quadratic placement based on search space traversing technology.

Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu

Integr., 2007

Voltage Island Generation in Cell Based Dual-Vdd Design.

Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.

Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Power Delivery Aware Floorplanning for Voltage Island Designs.

Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.

Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.

Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.

Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

New timing and routability driven placement algorithms for FPGA synthesis.

Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.

Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR.

Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Logic and Layout Aware Voltage Island Generation for Low Power Design.

Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani

ACM Trans. Design Autom. Electr. Syst., 2006

Multilevel Routing With Redundant Via Insertion.

Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment.

Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Priority-Based Routing Resource Assignment Considering Crosstalk.

Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong

J. Comput. Sci. Technol., 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng

Proceedings of the 2006 International Symposium on Physical Design, 2006

A novel low-power physical design methodology for MTCMOS.

Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.

Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.

Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.

Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Crosstalk-Aware Routing Resource Assignment.

Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong

J. Comput. Sci. Technol., 2005

Shielding Area Optimization Under the Solution of Interconnect Crosstalk.

Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong

J. Comput. Sci. Technol., 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Navigating Register Placement for Low Power Clock Network Design.

Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Crosstalk and Congestion Driven Layer Assignment Algorithm.

Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.

Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong

Proceedings of the Integrated Circuit and System Design, 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Integrated routing resource assignment for RLC crosstalk minimization.

Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.

Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong

Proceedings of the Advances in Natural Computation, First International Conference, 2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.

Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design.

Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou

Proceedings of the Computational Science and Its Applications, 2005

Improved multilevel routing with redundant via placement for yield and reliability.

Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new algorithm for layout of dark field alternating phase shifting masks.

Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Navigating registers in placement for clock network minimization.

Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu

Proceedings of the 42nd Design Automation Conference, 2005

Analysis of buffered hybrid structured clock networks.

Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.

Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.

Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Shielding area optimization under the solution of interconnect crosstalk.

Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk driven routing resource assignment.

Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.

Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Algorithm for yield driven correction of layout.

Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Layer assignment algorithm for RLC crosstalk minimization.

Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.

Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004