Felipe G. A. e Silva

According to our database1, Felipe G. A. e Silva authored at least 12 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
DEMC: A dynamic multi-ECC memory controller with per-block adaptation.
Integr., 2026

2023
A Triple Burst Error Correction Based on Region Selection Code.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Memory Controller with Adaptive ECC for Reliable System Operation.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2022
Expanding Column Line Code Adaptive (CLC-A) for Protecting 32-and 64-Bit Data.
IEEE Des. Test, 2022

2020
Optimized buffer protection for network-on-chip based on Error Correction Code.
Microelectron. J., 2020

CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

MMS: A Software for Error Monitoring in Memories Protected by ECC.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2019
Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays.
J. Electron. Test., 2018

2017
An efficient, low-cost ECC approach for critical-application memories.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Evaluation of multiple bit upset tolerant codes for NoCs buffering.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
A correction code for multiple cells upsets in memory devices for space applications.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016


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